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17 KiB
Plaintext
301 lines
17 KiB
Plaintext
Release 14.2 par P.28xd (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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EVALU157:: Fri Jul 19 19:14:05 2013
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par -w -intstyle ise -ol high -mt off fpga_map.ncd fpga.ncd fpga.pcf
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Constraints file: fpga.pcf.
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Loading device for application Rf_Device from file '7k325t.nph' in environment C:\Xilinx\14.2\ISE_DS\ISE\.
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"fpga" is an NCD, version 3.2, device xc7k325t, package ffg900, speed -2
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts)
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Device speed data version: "PRELIMINARY 1.06 2012-07-14".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 3,012 out of 407,600 1%
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Number used as Flip Flops: 3,011
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 1
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Number of Slice LUTs: 4,500 out of 203,800 2%
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Number used as logic: 4,444 out of 203,800 2%
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Number using O6 output only: 3,213
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Number using O5 output only: 357
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Number using O5 and O6: 874
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Number used as ROM: 0
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Number used as Memory: 2 out of 64,000 1%
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Number used as Dual Port RAM: 0
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Number used as Single Port RAM: 0
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Number used as Shift Register: 2
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Number using O6 output only: 2
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Number using O5 output only: 0
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Number using O5 and O6: 0
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Number used exclusively as route-thrus: 54
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Number with same-slice register load: 38
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Number with same-slice carry load: 16
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 1,794 out of 50,950 3%
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Number of LUT Flip Flop pairs used: 5,077
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Number with an unused Flip Flop: 2,306 out of 5,077 45%
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Number with an unused LUT: 577 out of 5,077 11%
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Number of fully used LUT-FF pairs: 2,194 out of 5,077 43%
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Number of slice register sites lost
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to control set restrictions: 0 out of 407,600 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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OVERMAPPING of BRAM resources should be ignored if the design is
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over-mapped for a non-BRAM resource or if placement fails.
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IO Utilization:
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Number of bonded IOBs: 28 out of 500 5%
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Number of LOCed IOBs: 28 out of 28 100%
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Number of bonded IPADs: 2
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Number of LOCed IPADs: 2 out of 2 100%
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Specific Feature Utilization:
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Number of RAMB36E1/FIFO36E1s: 24 out of 445 5%
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Number using RAMB36E1 only: 24
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Number using FIFO36E1 only: 0
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Number of RAMB18E1/FIFO18E1s: 5 out of 890 1%
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Number using RAMB18E1 only: 5
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Number using FIFO18E1 only: 0
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Number of BUFG/BUFGCTRLs: 7 out of 32 21%
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Number used as BUFGs: 7
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Number used as BUFGCTRLs: 0
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Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 500 0%
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Number of ILOGICE2/ILOGICE3/ISERDESE2s: 2 out of 500 1%
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Number used as ILOGICE2s: 0
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Number used as ILOGICE3s: 0
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Number used as ISERDESE2s: 2
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Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 150 0%
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Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 500 0%
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Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 40 0%
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Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 40 0%
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Number of BSCANs: 1 out of 4 25%
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Number of BUFHCEs: 0 out of 168 0%
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Number of BUFRs: 0 out of 40 0%
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Number of CAPTUREs: 0 out of 1 0%
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Number of DNA_PORTs: 0 out of 1 0%
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Number of DSP48E1s: 3 out of 840 1%
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Number of EFUSE_USRs: 0 out of 1 0%
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Number of FRAME_ECCs: 0 out of 1 0%
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Number of GTXE2_CHANNELs: 0 out of 16 0%
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Number of GTXE2_COMMONs: 0 out of 4 0%
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Number of ICAPs: 0 out of 2 0%
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Number of IDELAYCTRLs: 0 out of 10 0%
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Number of IN_FIFOs: 0 out of 40 0%
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Number of MMCME2_ADVs: 3 out of 10 30%
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Number of OUT_FIFOs: 0 out of 40 0%
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Number of PCIE_2_1s: 0 out of 1 0%
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Number of PHASER_REFs: 0 out of 10 0%
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Number of PHY_CONTROLs: 0 out of 10 0%
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Number of PLLE2_ADVs: 0 out of 10 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of XADCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 37 secs
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Finished initial Timing Analysis. REAL time: 37 secs
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Starting Router
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Phase 1 : 30990 unrouted; REAL time: 45 secs
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Phase 2 : 25439 unrouted; REAL time: 49 secs
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Phase 3 : 10120 unrouted; REAL time: 1 mins 7 secs
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Phase 4 : 10169 unrouted; (Setup:58605, Hold:15259, Component Switching Limit:0) REAL time: 1 mins 30 secs
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Updating file: fpga.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Setup:70266, Hold:12888, Component Switching Limit:0) REAL time: 1 mins 50 secs
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Phase 6 : 0 unrouted; (Setup:70266, Hold:12888, Component Switching Limit:0) REAL time: 1 mins 54 secs
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Phase 7 : 0 unrouted; (Setup:70266, Hold:12888, Component Switching Limit:0) REAL time: 1 mins 54 secs
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Phase 8 : 0 unrouted; (Setup:70266, Hold:12888, Component Switching Limit:0) REAL time: 1 mins 54 secs
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Phase 9 : 0 unrouted; (Setup:65286, Hold:0, Component Switching Limit:0) REAL time: 1 mins 58 secs
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Total REAL time to Router completion: 1 mins 59 secs
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Total CPU time to Router completion: 2 mins 2 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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|u0/u11/U_Wrapped_tdc | | | | | |
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|/Wrapped_tdc/U_Mux_t | | | | | |
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| dc/clk_0 | BUFGCTRL_X0Y1| No | 233 | 0.615 | 1.990 |
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+---------------------+--------------+------+------+------------+-------------+
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| clk_62_5_o | BUFGCTRL_X0Y5| No | 934 | 0.469 | 1.672 |
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+---------------------+--------------+------+------+------------+-------------+
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| s_o_OBUF | BUFGCTRL_X0Y2| No | 5 | 0.530 | 1.990 |
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+---------------------+--------------+------+------+------------+-------------+
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|u0/u11/U_Wrapped_tdc | | | | | |
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|/Wrapped_tdc/U_Mux_t | | | | | |
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|dc/dcm2/clkfbout_buf | | | | | |
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| | BUFGCTRL_X0Y0| No | 1 | 0.000 | 1.936 |
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+---------------------+--------------+------+------+------------+-------------+
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|u0/u11/U_Wrapped_tdc | | | | | |
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|/Wrapped_tdc/U_Mux_t | | | | | |
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| dc/clk0_in | BUFGCTRL_X0Y3| No | 1 | 0.000 | 1.936 |
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+---------------------+--------------+------+------+------------+-------------+
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|u0/u11/U_Wrapped_tdc | | | | | |
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|/Wrapped_tdc/U_Mux_t | | | | | |
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|dc/dcm250/clkfbout_b | | | | | |
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| uf | BUFGCTRL_X0Y4| No | 1 | 0.000 | 1.592 |
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+---------------------+--------------+------+------+------------+-------------+
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| u1/clkin1 |BUFGCTRL_X0Y31| No | 1 | 0.000 | 1.766 |
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+---------------------+--------------+------+------+------------+-------------+
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|u0/u0/gen_profile_me | | | | | |
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|dium_icache_debug.U_ | | | | | |
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| Wrapped_LM32/jtck | Local| | 7 | 0.319 | 1.303 |
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+---------------------+--------------+------+------+------------+-------------+
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| u1/clkfbout | Local| | 1 | 0.000 | 0.012 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 65286 (Setup: 65286, Hold: 0, Component Switching Limit: 0)
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WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
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Review the timing report using Timing Analyzer (In ISE select "Post-Place &
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Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
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Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
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are set in the tools for timing closure.
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Use the Xilinx "SmartXplorer" script to try special combinations of
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options known to produce very good results.
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Visit the Xilinx technical support web at http://support.xilinx.com and go to
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either "Troubleshoot->Tech Tips->Timing & Constraints" or "
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TechXclusives->Timing Closure" for tips and suggestions for meeting timing
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in your design.
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Number of Timing Constraints that were not applied: 3
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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* TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux | SETUP | -1.473ns| 5.473ns| 131| 65286
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_tdc_dcm2_clkout0 = PERIOD TIMEGRP | HOLD | 0.008ns| | 0| 0
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux | | | | |
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_tdc_dcm2_clkout0" TS_u0_u11_U_Wr | | | | |
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apped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_cl | | | | |
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kout0 HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout | SETUP | 0.937ns| 12.252ns| 0| 0
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0" TS_ClkI_p / 0.5 HIGH 50% | HOLD | 0.040ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux | MINLOWPULSE | 1.666ns| 2.334ns| 0| 0
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_tdc_dcm250_clkout0 = PERIOD TIMEGRP | | | | |
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_M | | | | |
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ux_tdc_dcm250_clkout0" TS_u1_clko | | | | |
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ut0 / 4 HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux | MINPERIOD | 2.592ns| 1.408ns| 0| 0
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_tdc_dcm2_clkout1 = PERIOD TIMEGRP | | | | |
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux | | | | |
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_tdc_dcm2_clkout1" TS_u0_u11_U_Wr | | | | |
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apped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_cl | | | | |
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kout0 PHASE 1 ns HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns | MINLOWPULSE | 4.000ns| 4.000ns| 0| 0
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HIGH 50% | | | | |
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----------------------------------------------------------------------------------------------------------
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Derived Constraint Report
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Review Timing Report for more details on the following derived constraints.
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To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
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or "Run Timing Analysis" from Timing Analyzer (timingan).
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Derived Constraints for TS_ClkI_p
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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| | Period | Actual Period | Timing Errors | Paths Analyzed |
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| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
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| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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|TS_ClkI_p | 8.000ns| 4.000ns| 10.946ns| 0| 131| 0| 1774656|
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| TS_u1_clkout0 | 16.000ns| 12.252ns| 21.892ns| 0| 131| 1696795| 77861|
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| TS_u0_u11_U_Wrapped_tdc_Wrapp| 4.000ns| 2.334ns| 5.473ns| 0| 131| 0| 77861|
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| ed_tdc_U_Mux_tdc_dcm250_clkou| | | | | | | |
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| t0 | | | | | | | |
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| TS_u0_u11_U_Wrapped_tdc_Wrap| 4.000ns| 1.408ns| N/A| 0| 0| 0| 0|
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| ped_tdc_U_Mux_tdc_dcm2_clkou| | | | | | | |
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| t1 | | | | | | | |
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| TS_u0_u11_U_Wrapped_tdc_Wrap| 4.000ns| 5.473ns| N/A| 131| 0| 77861| 0|
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| ped_tdc_U_Mux_tdc_dcm2_clkou| | | | | | | |
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| t0 | | | | | | | |
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+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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1 constraint not met.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 2 mins 4 secs
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Total CPU time to PAR completion: 2 mins 8 secs
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Peak Memory Usage: 756 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - 131 errors found.
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Number of error messages: 0
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Number of warning messages: 1
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Number of info messages: 0
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Writing design to file fpga.ncd
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PAR done!
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