You've already forked gitified_old_clb_svn
10107 lines
612 KiB
Plaintext
10107 lines
612 KiB
Plaintext
//! **************************************************************************
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// Written by: Map P.28xd on Fri Jul 19 19:13:58 2013
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//! **************************************************************************
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SCHEMATIC START;
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COMP "Spy2" LOCATE = SITE "AF20" LEVEL 1;
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COMP "Spy3" LOCATE = SITE "AH21" LEVEL 1;
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COMP "sRx" LOCATE = SITE "M19" LEVEL 1;
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COMP "sTx" LOCATE = SITE "K24" LEVEL 1;
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COMP "s_o" LOCATE = SITE "K25" LEVEL 1;
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COMP "ss2" LOCATE = SITE "L25" LEVEL 1;
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COMP "sw" LOCATE = SITE "G12" LEVEL 1;
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COMP "RST_I" LOCATE = SITE "AB12" LEVEL 1;
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COMP "Blink" LOCATE = SITE "F16" LEVEL 1;
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COMP "GPIO_LED<2>" LOCATE = SITE "AC9" LEVEL 1;
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COMP "GPIO_LED<1>" LOCATE = SITE "AA8" LEVEL 1;
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COMP "GPIO_LED<4>" LOCATE = SITE "AE26" LEVEL 1;
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COMP "GPIO_LED<3>" LOCATE = SITE "AB9" LEVEL 1;
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COMP "GPIO_LED<0>" LOCATE = SITE "AB8" LEVEL 1;
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COMP "GPIO_LED<6>" LOCATE = SITE "E18" LEVEL 1;
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COMP "GPIO_LED<5>" LOCATE = SITE "G19" LEVEL 1;
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COMP "irq_0" LOCATE = SITE "AC6" LEVEL 1;
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COMP "irq_1" LOCATE = SITE "AG5" LEVEL 1;
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COMP "pad_mosi_o" LOCATE = SITE "P24" LEVEL 1;
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COMP "ClkI_n" LOCATE = SITE "G7" LEVEL 1;
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COMP "ClkI_p" LOCATE = SITE "G8" LEVEL 1;
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COMP "s<0>" LOCATE = SITE "Y23" LEVEL 1;
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COMP "scl1" LOCATE = SITE "D28" LEVEL 1;
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COMP "scl2" LOCATE = SITE "K21" LEVEL 1;
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COMP "sda1" LOCATE = SITE "E28" LEVEL 1;
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COMP "sda2" LOCATE = SITE "L21" LEVEL 1;
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COMP "pad_sclk_o" LOCATE = SITE "R24" LEVEL 1;
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COMP "pad_cs_o" LOCATE = SITE "U19" LEVEL 1;
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COMP "pad_miso_i" LOCATE = SITE "R25" LEVEL 1;
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COMP "s_n<0>" LOCATE = SITE "Y24" LEVEL 1;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0056_pins<64>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0056"
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PINNAME CLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0055_pins<112>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0055"
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PINNAME CLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Mmult_a0[15]_b0[15]_MuLt_9_OUT_pins<64>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Mmult_a0[15]_b0[15]_MuLt_9_OUT"
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PINNAME CLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem_pins<33>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem"
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PINNAME CLKBWRCLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram_pins<33>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram"
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PINNAME CLKBWRCLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram_pins<33>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram"
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PINNAME CLKBWRCLK;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<63>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem"
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PINNAME CLKARDCLKU;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<62>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem"
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PINNAME CLKARDCLKL;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<65>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem"
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PINNAME CLKBWRCLKU;
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PIN
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u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<64>
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= BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem"
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PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4" PINNAME CLKARDCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<65> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4" PINNAME CLKBWRCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<64> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4" PINNAME CLKBWRCLKL;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<63> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5" PINNAME CLKARDCLKU;
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PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<62> = BEL
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"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5" PINNAME CLKARDCLKL;
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|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<65> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5" PINNAME CLKBWRCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<64> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5" PINNAME CLKBWRCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<63> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6" PINNAME CLKARDCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<62> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6" PINNAME CLKARDCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<65> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6" PINNAME CLKBWRCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<64> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6" PINNAME CLKBWRCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<63> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7" PINNAME CLKARDCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<62> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7" PINNAME CLKARDCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<65> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7" PINNAME CLKBWRCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<64> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7" PINNAME CLKBWRCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<63> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8" PINNAME CLKARDCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<62> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8" PINNAME CLKARDCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<65> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8" PINNAME CLKBWRCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<64> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8" PINNAME CLKBWRCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<63> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9" PINNAME CLKARDCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<62> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9" PINNAME CLKARDCLKL;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<65> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9" PINNAME CLKBWRCLKU;
|
|
PIN u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<64> = BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9" PINNAME CLKBWRCLKL;
|
|
PIN u0_u9/rom/Mram_rom_pins<63> = BEL "u0_u9/rom/Mram_rom" PINNAME CLKARDCLKU;
|
|
PIN u0_u9/rom/Mram_rom_pins<62> = BEL "u0_u9/rom/Mram_rom" PINNAME CLKARDCLKL;
|
|
PIN u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst_pins<2> =
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst"
|
|
PINNAME CLKIN1;
|
|
TIMEGRP u1_clkout0 = BEL "u7/u1/O" BEL "u7/u0/O" BEL "u3/Count_0" BEL
|
|
"u3/Count_1" BEL "u3/Count_2" BEL "u3/Count_3" BEL "u3/Count_4" BEL
|
|
"u3/Count_5" BEL "u3/Count_6" BEL "u3/Count_7" BEL "u3/Count_8" BEL
|
|
"u3/Count_9" BEL "u3/Count_10" BEL "u3/Count_11" BEL "u3/Count_12" BEL
|
|
"u3/Count_13" BEL "u3/Count_14" BEL "u3/Count_15" BEL "u3/Count_16"
|
|
BEL "u3/Count_17" BEL "u3/Count_18" BEL "u3/Count_19" BEL
|
|
"u3/Count_20" BEL "u3/Count_21" BEL "u3/Count_22" BEL "u3/Count_23"
|
|
BEL "u3/Count_24" BEL "u1/clk_65_5_buf" BEL "u0/u0/data_addr_reg_17"
|
|
BEL "u0/u0/data_addr_reg_16" BEL "u0/u0/data_addr_reg_15" BEL
|
|
"u0/u0/data_addr_reg_14" BEL "u0/u0/data_addr_reg_13" BEL
|
|
"u0/u0/data_addr_reg_12" BEL "u0/u0/data_addr_reg_11" BEL
|
|
"u0/u0/data_addr_reg_10" BEL "u0/u0/data_addr_reg_9" BEL
|
|
"u0/u0/data_addr_reg_8" BEL "u0/u0/data_addr_reg_7" BEL
|
|
"u0/u0/data_addr_reg_6" BEL "u0/u0/data_addr_reg_5" BEL
|
|
"u0/u0/data_addr_reg_4" BEL "u0/u0/data_addr_reg_3" BEL
|
|
"u0/u0/data_addr_reg_2" BEL "u0/u0/inst_addr_reg_17" BEL
|
|
"u0/u0/inst_addr_reg_16" BEL "u0/u0/inst_addr_reg_15" BEL
|
|
"u0/u0/inst_addr_reg_14" BEL "u0/u0/inst_addr_reg_13" BEL
|
|
"u0/u0/inst_addr_reg_12" BEL "u0/u0/inst_addr_reg_11" BEL
|
|
"u0/u0/inst_addr_reg_10" BEL "u0/u0/inst_addr_reg_9" BEL
|
|
"u0/u0/inst_addr_reg_8" BEL "u0/u0/inst_addr_reg_7" BEL
|
|
"u0/u0/inst_addr_reg_6" BEL "u0/u0/inst_addr_reg_5" BEL
|
|
"u0/u0/inst_addr_reg_4" BEL "u0/u0/inst_addr_reg_3" BEL
|
|
"u0/u0/inst_addr_reg_2" BEL "u0/u0/data_remaining_0" BEL
|
|
"u0/u0/inst_remaining_2" BEL "u0/u0/inst_remaining_1" BEL
|
|
"u0/u0/inst_remaining_0" BEL "u0/u0/inst_was_busy" BEL
|
|
"u0/u0/data_was_busy" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_w"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_bypass_enable_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_write_enable_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/bret_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eret_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/break_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/scall_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_4"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_3"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_2"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_1"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_bypass_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_bypass_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_met_m"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_30"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_29"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_28"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_27"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_26"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_25"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_24"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_23"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_22"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_21"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_20"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_19"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_18"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_17"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_16"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_15"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_14"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_13"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_12"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_11"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_10"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_9"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_8"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_30"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_29"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_28"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_27"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_26"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_25"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_24"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_23"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_22"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_21"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_20"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_19"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_18"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_17"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_16"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_15"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_14"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_13"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_12"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_11"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_10"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_9"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_29"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_26"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_25"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_23"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_22"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_21"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_20"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_5"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_taken_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_taken_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_w"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_w"
|
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_m"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_compare_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_shift_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_31"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_30"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_29"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_26"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_25"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_24"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_23"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_22"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_21"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_20"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_19"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_18"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_17"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_16"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_15"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_14"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_11"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_10"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_9"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_8"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_7"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_6"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_5"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/debug_exception_w"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/non_debug_exception_w"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/non_debug_exception_m"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/debug_exception_m"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/exception_m"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/adder_op_x_n"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/adder_op_x"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_x"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_shift_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_compare_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_add_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_sext_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_csr_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/regfile_raw_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_31"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_30"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_29"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_26"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_25"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_24"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_23"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_22"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_21"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_20"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_19"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_18"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_17"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_16"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_15"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_14"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_11"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_10"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_9"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_8"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_7"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/regfile_raw_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ip_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ip_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_10"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_9"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_8"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_7"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_6"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_5"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_4"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_0"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_29"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_28"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_27"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_26"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_23"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_22"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_14"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_4"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_3"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_valid"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_valid"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_2"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_5"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_4"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_31"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_30"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_29"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_28"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_27"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_26"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_24"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_23"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_22"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_21"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_20"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_19"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_18"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_17"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_16"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_15"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_14"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_13"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_12"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_11"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_10"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_9"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_8"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_7"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_6"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_5"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_4"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_3"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_0"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_30"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_29"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_28"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_27"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_26"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_23"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_22"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_21"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_20"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_19"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_18"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_17"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_6"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_14"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_13"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_12"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_11"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_10"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_9"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_7"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_6"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_5"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_4"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_2"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_28"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_26"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_25"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_24"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_23"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_22"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_21"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_ready"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refilling"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_offset_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_offset_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/restart_request"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_29"
|
|
BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_26"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_25"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_24"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_23"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_22"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_21"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_20"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_19"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_18"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_17"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_16"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_15"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_14"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_13"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_12"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_11"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_10"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_9"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_8"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_7"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_6"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_5"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_4"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_3"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_0"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_31"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_30"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_29"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_28"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_26"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_25"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_24"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_23"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_22"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_21"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_20"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_19"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_18"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_17"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_16"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_15"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_14"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_13"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_12"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_11"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_10"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_9"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_8"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_7"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_6"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_5"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_4"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_3"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/sign_extend_w"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_31"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_30"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_29"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_27"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_26"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_25"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_24"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_23"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_22"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_21"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_20"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_19"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_18"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_17"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_16"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_15"
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_14"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_13"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_12"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_11"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_10"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_9"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_8"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_7"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_6"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_5"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_4"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_3"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_0"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_w_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_w_0"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_3"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_0"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/sign_extend_m"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_31"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_30"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_29"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_27"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_26"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_25"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_24"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_23"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_22"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_21"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_20"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_19"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_18"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_17"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_16"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_15"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_14"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_13"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_12"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_10"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_9"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_8"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_7"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_6"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_5"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_4"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_3"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_2"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_1"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_0"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_16"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_15"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_14"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_13"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_12"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_6"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_5"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_m_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_m_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_29"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_28"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_27"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_26"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_18"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_17"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_15"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_14"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_13"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_12"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_1"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_0"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/direction_m"
|
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PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0056_pins<64>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0055_pins<112>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Mmult_a0[15]_b0[15]_MuLt_9_OUT_pins<64>"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_5"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_6"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_7"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_8"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_9"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_10"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_11"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_14"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_15"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/dc_ss"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_313"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_303"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_293"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_283"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_273"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_263"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_253"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_243"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_233"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_223"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_215"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_203"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_193"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_183"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_173"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_163"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_153"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_143"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_133"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_123"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_115"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_103"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_93"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_83"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_73"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_63"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_53"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_43"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_34"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_214"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_114"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_03"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_312"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_302"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_292"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_282"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_272"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_262"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_252"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_242"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_232"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_222"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_213"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_202"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_192"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_182"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_172"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_162"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_152"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_142"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_132"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_122"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_113"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_102"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_92"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_82"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_72"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_62"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_52"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_42"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_33"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_212"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_112"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_02"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_311"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_301"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_291"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_281"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_271"
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_261"
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|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_251"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_241"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_231"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_221"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_211"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_201"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_191"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_181"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_171"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_161"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_151"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_141"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_131"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_121"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_111"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_101"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_91"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_81"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_71"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_61"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_51"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_41"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_32"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_210"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_110"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_01"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/dc_re"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<3>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<2>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<3>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<2>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<1>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<1>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<0>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<0>_1"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/iack_o" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_0" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_1" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_2" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_3" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_4" BEL
|
|
"u0/u1/crossbar/matrix_old_0_3" BEL "u0/u1/crossbar/matrix_old_0_2"
|
|
BEL "u0/u1/crossbar/matrix_old_0_1" BEL
|
|
"u0/u1/crossbar/matrix_old_0_0" BEL "u0/u1/crossbar/matrix_old_1_3"
|
|
BEL "u0/u1/crossbar/matrix_old_1_2" BEL
|
|
"u0/u1/crossbar/matrix_old_1_1" BEL "u0/u1/crossbar/matrix_old_1_0"
|
|
BEL "u0/u1/rom/adr_reg_5" BEL "u0/u1/rom/adr_reg_4" BEL
|
|
"u0/u1/rom/adr_reg_3" BEL "u0/u1/rom/adr_reg_2" BEL
|
|
"u0/u1/rom/adr_reg_1" BEL "u0/u1/rom/adr_reg_0" BEL
|
|
"u0/u9/crossbar/matrix_old_0_17" BEL "u0/u9/crossbar/matrix_old_0_16"
|
|
BEL "u0/u9/crossbar/matrix_old_0_15" BEL
|
|
"u0/u9/crossbar/matrix_old_0_14" BEL "u0/u9/crossbar/matrix_old_0_13"
|
|
BEL "u0/u9/crossbar/matrix_old_0_12" BEL
|
|
"u0/u9/crossbar/matrix_old_0_11" BEL "u0/u9/crossbar/matrix_old_0_10"
|
|
BEL "u0/u9/crossbar/matrix_old_0_9" BEL
|
|
"u0/u9/crossbar/matrix_old_0_8" BEL "u0/u9/crossbar/matrix_old_0_7"
|
|
BEL "u0/u9/crossbar/matrix_old_0_6" BEL
|
|
"u0/u9/crossbar/matrix_old_0_5" BEL "u0/u9/crossbar/matrix_old_0_4"
|
|
BEL "u0/u9/crossbar/matrix_old_0_3" BEL
|
|
"u0/u9/crossbar/matrix_old_0_2" BEL "u0/u9/crossbar/matrix_old_0_1"
|
|
BEL "u0/u9/crossbar/matrix_old_0_0" BEL "u0/u9/crossbar/virtual_ERR"
|
|
BEL "u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_7" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_6" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_5" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_4" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_3" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_2" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_1" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_0" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_16" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_15" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_14" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_13" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_12" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_11" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_10" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_9" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_8" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_7" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_6" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_5" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_4" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_3" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_2" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_1" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_0" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/ack_sreg" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_16"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_15"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_14"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_13"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_12"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_11"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_10"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_9"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_8"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_7"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_6"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_5"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_4"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_3"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_2"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_1"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_0"
|
|
BEL "u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_cnt_inv_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_cnt_inv_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_sync_inv_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_sync_inv_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_0" BEL
|
|
"u0/u3/U_Tics/cntr_tics_31" BEL "u0/u3/U_Tics/cntr_tics_30" BEL
|
|
"u0/u3/U_Tics/cntr_tics_29" BEL "u0/u3/U_Tics/cntr_tics_28" BEL
|
|
"u0/u3/U_Tics/cntr_tics_27" BEL "u0/u3/U_Tics/cntr_tics_26" BEL
|
|
"u0/u3/U_Tics/cntr_tics_25" BEL "u0/u3/U_Tics/cntr_tics_24" BEL
|
|
"u0/u3/U_Tics/cntr_tics_23" BEL "u0/u3/U_Tics/cntr_tics_22" BEL
|
|
"u0/u3/U_Tics/cntr_tics_21" BEL "u0/u3/U_Tics/cntr_tics_20" BEL
|
|
"u0/u3/U_Tics/cntr_tics_19" BEL "u0/u3/U_Tics/cntr_tics_18" BEL
|
|
"u0/u3/U_Tics/cntr_tics_17" BEL "u0/u3/U_Tics/cntr_tics_16" BEL
|
|
"u0/u3/U_Tics/cntr_tics_15" BEL "u0/u3/U_Tics/cntr_tics_14" BEL
|
|
"u0/u3/U_Tics/cntr_tics_13" BEL "u0/u3/U_Tics/cntr_tics_12" BEL
|
|
"u0/u3/U_Tics/cntr_tics_11" BEL "u0/u3/U_Tics/cntr_tics_10" BEL
|
|
"u0/u3/U_Tics/cntr_tics_9" BEL "u0/u3/U_Tics/cntr_tics_8" BEL
|
|
"u0/u3/U_Tics/cntr_tics_7" BEL "u0/u3/U_Tics/cntr_tics_6" BEL
|
|
"u0/u3/U_Tics/cntr_tics_5" BEL "u0/u3/U_Tics/cntr_tics_4" BEL
|
|
"u0/u3/U_Tics/cntr_tics_3" BEL "u0/u3/U_Tics/cntr_tics_2" BEL
|
|
"u0/u3/U_Tics/cntr_tics_1" BEL "u0/u3/U_Tics/cntr_tics_0" BEL
|
|
"u0/u3/U_Tics/cntr_div_23" BEL "u0/u3/U_Tics/cntr_div_22" BEL
|
|
"u0/u3/U_Tics/cntr_div_21" BEL "u0/u3/U_Tics/cntr_div_20" BEL
|
|
"u0/u3/U_Tics/cntr_div_19" BEL "u0/u3/U_Tics/cntr_div_18" BEL
|
|
"u0/u3/U_Tics/cntr_div_17" BEL "u0/u3/U_Tics/cntr_div_16" BEL
|
|
"u0/u3/U_Tics/cntr_div_15" BEL "u0/u3/U_Tics/cntr_div_14" BEL
|
|
"u0/u3/U_Tics/cntr_div_13" BEL "u0/u3/U_Tics/cntr_div_12" BEL
|
|
"u0/u3/U_Tics/cntr_div_11" BEL "u0/u3/U_Tics/cntr_div_10" BEL
|
|
"u0/u3/U_Tics/cntr_div_9" BEL "u0/u3/U_Tics/cntr_div_8" BEL
|
|
"u0/u3/U_Tics/cntr_div_7" BEL "u0/u3/U_Tics/cntr_div_6" BEL
|
|
"u0/u3/U_Tics/cntr_div_5" BEL "u0/u3/U_Tics/cntr_div_4" BEL
|
|
"u0/u3/U_Tics/cntr_div_3" BEL "u0/u3/U_Tics/cntr_div_2" BEL
|
|
"u0/u3/U_Tics/cntr_div_1" BEL "u0/u3/U_Tics/cntr_div_0" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_31" BEL "u0/u3/U_Tics/wb_out_dat_30" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_29" BEL "u0/u3/U_Tics/wb_out_dat_28" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_27" BEL "u0/u3/U_Tics/wb_out_dat_26" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_25" BEL "u0/u3/U_Tics/wb_out_dat_24" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_23" BEL "u0/u3/U_Tics/wb_out_dat_22" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_21" BEL "u0/u3/U_Tics/wb_out_dat_20" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_19" BEL "u0/u3/U_Tics/wb_out_dat_18" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_17" BEL "u0/u3/U_Tics/wb_out_dat_16" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_15" BEL "u0/u3/U_Tics/wb_out_dat_14" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_13" BEL "u0/u3/U_Tics/wb_out_dat_12" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_11" BEL "u0/u3/U_Tics/wb_out_dat_10" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_9" BEL "u0/u3/U_Tics/wb_out_dat_8" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_7" BEL "u0/u3/U_Tics/wb_out_dat_6" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_5" BEL "u0/u3/U_Tics/wb_out_dat_4" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_3" BEL "u0/u3/U_Tics/wb_out_dat_2" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_1" BEL "u0/u3/U_Tics/wb_out_dat_0" BEL
|
|
"u0/u3/U_Tics/cntr_overflow" BEL "u0/u5/Wrapped_GPIO/wb_out_dat_31"
|
|
BEL "u0/u5/Wrapped_GPIO/wb_out_dat_30" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_29" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_28" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_27" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_26" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_25" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_24" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_23" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_22" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_21" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_20" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_19" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_18" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_17" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_16" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_15" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_14" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_13" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_12" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_11" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_10" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_9" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_8" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_7" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_6" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_5" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_4" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_3" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_2" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_1" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_0" BEL "u0/u5/Wrapped_GPIO/dir_reg_31"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_30" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_29" BEL "u0/u5/Wrapped_GPIO/dir_reg_28"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_27" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_26" BEL "u0/u5/Wrapped_GPIO/dir_reg_25"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_24" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_23" BEL "u0/u5/Wrapped_GPIO/dir_reg_22"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_21" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_20" BEL "u0/u5/Wrapped_GPIO/dir_reg_19"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_18" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_17" BEL "u0/u5/Wrapped_GPIO/dir_reg_16"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_15" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_14" BEL "u0/u5/Wrapped_GPIO/dir_reg_13"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_12" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_11" BEL "u0/u5/Wrapped_GPIO/dir_reg_10"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_9" BEL "u0/u5/Wrapped_GPIO/dir_reg_8"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_7" BEL "u0/u5/Wrapped_GPIO/dir_reg_6"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_5" BEL "u0/u5/Wrapped_GPIO/dir_reg_4"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_3" BEL "u0/u5/Wrapped_GPIO/dir_reg_2"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_1" BEL "u0/u5/Wrapped_GPIO/dir_reg_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/rxack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_15" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_14" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_13" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_12" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_11" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_10" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_9" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_8" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/irq_flag" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/al" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/tip" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/iack_o" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/rxack" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_15" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_14" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_13" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_12" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_11" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_10" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_9" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_8" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/irq_flag" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/al" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/tip" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/iack_o" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/shift" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_txd" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ld" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/host_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/shift" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_txd" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ld" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/host_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_15" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_14" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_13" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_12" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_11" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_10" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_9" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_8" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd3"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd4"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd5"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cmd_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/ial" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dscl_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_0"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSDA" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSCL" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_13"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_12"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_11"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_10"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_9"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_8"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_7"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_6"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_5"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_4"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_3"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSDA" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSCL" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sto_condition"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.ibusy"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/clk_en" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_15" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_14" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_13" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_12" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_11" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_10" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_9" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_8" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd3"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd4"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd5"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cmd_ack" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/ial" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dscl_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_0"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSDA" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSCL" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_13"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_12"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_11"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_10"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_9"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_8"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_7"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_6"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_5"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_4"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_3"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSDA" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSCL" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sto_condition"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.ibusy"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/clk_en" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_31" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_30" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_29" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_28" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_27" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_26" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_25" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_24" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_23" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_22" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_21" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_20" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_19" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_18" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_17" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_16" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_ack_o" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/neg_edge" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/pos_edge" BEL
|
|
"u0/u15/Wrapped_date_rev_id/ack_int" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_0"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/use_buf"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reset"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_break"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/jtag_access"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cyc_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/stall_wb_load"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_we_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_stb_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_select_m"
|
|
BEL "u0/u14/U_Wrapped_I2C/U_Adapter/fsm_state" BEL
|
|
"u0/u7/U_Wrapped_I2C/U_Adapter/fsm_state" BEL
|
|
"u0/u11/U_Wrapped_tdc/U_Adapter/fsm_state" BEL
|
|
"u0/u12/U_Wrapped_UART/U_Adapter/fsm_state" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_sr_rx_rdy_i" BEL
|
|
"u0/u3/U_Tics/U_Adapter/fsm_state" BEL
|
|
"u0/u5/Wrapped_GPIO/U_Adapter/fsm_state" BEL
|
|
"u0/u5/Wrapped_GPIO/ack_int" BEL
|
|
"u0/u18/U_Wrapped_SPI/U_Adapter/fsm_state" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/bie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_write_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_csr_write_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/processing"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_read_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cti_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_we_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_load_complete"
|
|
BEL "u0/u12/U_Wrapped_UART/U_WB_SLAVE/rdr_rack_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_host_tdr_data_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_tdr_tx_data_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_bcr_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_bit_inv" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ack_out" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ack_out" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sda_chk" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dout" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sda_chk" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dout" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop"
|
|
BEL "u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_16" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_17" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_18" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_19" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_20" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_21" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_22" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_23" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_25" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_26" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_24" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_27" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_28" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_29" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_30" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_31" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_32" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_33" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_34" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_35" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_36" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_37" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_38" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_39" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_40" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_42" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_43" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_41" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_44" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_45" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_46" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_47" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_48" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_49" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_51" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_52" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_50" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_53" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_54" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_55" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_56" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_57" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_58" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_60" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_61" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_59" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_62" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_63" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_64" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_65" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_66" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_67" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_68" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_69" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_70" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_71" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_72" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_73" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_74" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_75" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_77" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_78" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_76" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_79" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_80" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_81" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_82" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_83" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_84" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_85" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_86" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_87" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_88" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_89" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_90" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_91" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_92" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_94" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_95" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_93" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_96" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_97" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_98" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_99" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_100" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_101" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_102" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_103" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_104" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_105" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_106" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_107" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_108" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_109" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_111" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_112" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_110" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_113" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_114" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_115" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_116" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_117" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_118" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_120" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_121" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_119" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_122" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_123" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_124" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_125" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_126" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_127" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/tip" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_f" BEL
|
|
"u7/u1/O_n" BEL "u0/u9/rom/slave_o_ack" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_w" BEL
|
|
"u0/u14/U_Wrapped_I2C/U_Adapter/stored_we" BEL
|
|
"u0/u7/U_Wrapped_I2C/U_Adapter/stored_we" BEL
|
|
"u0/u11/U_Wrapped_tdc/U_Adapter/stored_we" BEL "u0/u4/slave1_out_ack"
|
|
BEL "u0/u1/crossbar/virtual_ERR" BEL "u0/u1/rom/slave_o_ack" BEL
|
|
"u0/u12/U_Wrapped_UART/U_Adapter/stored_we" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_ready" BEL
|
|
"u0/u3/U_Tics/U_Adapter/stored_we" BEL "u0/u3/U_Tics/wb_out_ack" BEL
|
|
"u0/u5/Wrapped_GPIO/U_Adapter/stored_we" BEL
|
|
"u0/u18/U_Wrapped_SPI/U_Adapter/stored_we" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_x" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_d" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_m" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cyc_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/exception_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_3_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4_1"
|
|
BEL "u8/u1/Mshreg_O" BEL "u8/u1/O" BEL "u6/u1/Mshreg_O" BEL "u6/u1/O"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem_pins<33>"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram_pins<33>"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram_pins<33>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<63>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<62>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<65>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<64>"
|
|
PIN "u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<64>" PIN
|
|
"u0_u9/rom/Mram_rom_pins<63>" PIN "u0_u9/rom/Mram_rom_pins<62>" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst_pins<2>";
|
|
TIMEGRP u1_clkout0_0 = BEL "u7/u1/O" BEL "u7/u0/O" BEL "u3/Count_0" BEL
|
|
"u3/Count_1" BEL "u3/Count_2" BEL "u3/Count_3" BEL "u3/Count_4" BEL
|
|
"u3/Count_5" BEL "u3/Count_6" BEL "u3/Count_7" BEL "u3/Count_8" BEL
|
|
"u3/Count_9" BEL "u3/Count_10" BEL "u3/Count_11" BEL "u3/Count_12" BEL
|
|
"u3/Count_13" BEL "u3/Count_14" BEL "u3/Count_15" BEL "u3/Count_16"
|
|
BEL "u3/Count_17" BEL "u3/Count_18" BEL "u3/Count_19" BEL
|
|
"u3/Count_20" BEL "u3/Count_21" BEL "u3/Count_22" BEL "u3/Count_23"
|
|
BEL "u3/Count_24" BEL "u1/clk_65_5_buf" BEL "u0/u0/data_addr_reg_17"
|
|
BEL "u0/u0/data_addr_reg_16" BEL "u0/u0/data_addr_reg_15" BEL
|
|
"u0/u0/data_addr_reg_14" BEL "u0/u0/data_addr_reg_13" BEL
|
|
"u0/u0/data_addr_reg_12" BEL "u0/u0/data_addr_reg_11" BEL
|
|
"u0/u0/data_addr_reg_10" BEL "u0/u0/data_addr_reg_9" BEL
|
|
"u0/u0/data_addr_reg_8" BEL "u0/u0/data_addr_reg_7" BEL
|
|
"u0/u0/data_addr_reg_6" BEL "u0/u0/data_addr_reg_5" BEL
|
|
"u0/u0/data_addr_reg_4" BEL "u0/u0/data_addr_reg_3" BEL
|
|
"u0/u0/data_addr_reg_2" BEL "u0/u0/inst_addr_reg_17" BEL
|
|
"u0/u0/inst_addr_reg_16" BEL "u0/u0/inst_addr_reg_15" BEL
|
|
"u0/u0/inst_addr_reg_14" BEL "u0/u0/inst_addr_reg_13" BEL
|
|
"u0/u0/inst_addr_reg_12" BEL "u0/u0/inst_addr_reg_11" BEL
|
|
"u0/u0/inst_addr_reg_10" BEL "u0/u0/inst_addr_reg_9" BEL
|
|
"u0/u0/inst_addr_reg_8" BEL "u0/u0/inst_addr_reg_7" BEL
|
|
"u0/u0/inst_addr_reg_6" BEL "u0/u0/inst_addr_reg_5" BEL
|
|
"u0/u0/inst_addr_reg_4" BEL "u0/u0/inst_addr_reg_3" BEL
|
|
"u0/u0/inst_addr_reg_2" BEL "u0/u0/data_remaining_0" BEL
|
|
"u0/u0/inst_remaining_2" BEL "u0/u0/inst_remaining_1" BEL
|
|
"u0/u0/inst_remaining_0" BEL "u0/u0/inst_was_busy" BEL
|
|
"u0/u0/data_was_busy" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_w"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_bypass_enable_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_write_enable_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/bret_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eret_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/break_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/scall_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_x"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_4"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_3"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_2"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_1"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/csr_x_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_bypass_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_bypass_enable_x"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_target_x_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_0_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_24"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_22"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_21"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_w_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_m_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_met_m"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_30"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_29"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_28"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_27"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_26"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_25"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_24"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_23"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_22"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_21"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_20"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_19"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_18"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_17"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_16"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_15"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_14"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_13"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_12"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_11"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_10"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_9"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/deba_8"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_30"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_29"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_28"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_27"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_26"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_25"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_24"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_23"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_22"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_21"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_20"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_19"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_18"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_17"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_16"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_15"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_14"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_13"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_12"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_11"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_10"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_9"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/eba_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_16"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_29"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_28"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_27"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_26"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_operand_x_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_29"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_28"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_27"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_26"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_data_buf_1_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_taken_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_w_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_taken_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_w"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_w"
|
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_m"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_compare_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_shift_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_31"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_30"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_29"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_28"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_27"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_26"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_25"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_24"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_23"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_22"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_21"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_20"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_19"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_18"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_17"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_16"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_15"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_14"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_11"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_10"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_9"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_8"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_7"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_6"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_5"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_0_x_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/debug_exception_w"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/non_debug_exception_w"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/non_debug_exception_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/debug_exception_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/exception_m"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_2"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_1"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_0"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/branch_predict_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_3"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/adder_op_x_n"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/adder_op_x"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_x"
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BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/store_x"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_4"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_3"
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_2"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_x_0"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_x"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_shift_x"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/m_result_sel_compare_x"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_add_x"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_sext_x"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/x_result_sel_csr_x"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/regfile_raw_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_31"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_29"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_28"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_27"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_26"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_25"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_17"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_13"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_12"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_10"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_6"
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_d_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/regfile_raw_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ip_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ip_0"
|
|
BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_10"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_9"
|
|
BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_8"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_7"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_6"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_5"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_4"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_3"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_2"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_1"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie_delay_0"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_31"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_30"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_29"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_28"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_27"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_26"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_25"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_24"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_23"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_22"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_21"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_20"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_19"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_18"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_17"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_16"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_15"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_14"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_13"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_12"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_9"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_8"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_7"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_6"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_2"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_1"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/im_0"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_valid"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_valid"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_0"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_3"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_2"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/instruction_d_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/restart_address_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_f_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_ready"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_x_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_d_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache_refill_data_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/flush_set_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refilling"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_offset_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_offset_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/refill_address_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/restart_request"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_22"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_21"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_20"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_19"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_18"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_17"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_13"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_12"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_11"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_10"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_9"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_8"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_7"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_6"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_5"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_4"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_dat_o_0"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_31"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_19"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_15"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_14"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_13"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_12"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_11"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_10"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_9"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_8"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_7"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_6"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_5"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_4"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/store_data_m_0"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_3"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_2"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_1"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_sel_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/sign_extend_w"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/data_w_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_w_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_w_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_3"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_2"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_1"
|
|
BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/byte_enable_m_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/sign_extend_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/size_m_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/direction_m"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0056_pins<64>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Maddsub_n0055_pins<112>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/Mmult_a0[15]_b0[15]_MuLt_9_OUT_pins<64>"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_0"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_1"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_2"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_3"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_4"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_5"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_6"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_7"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_8"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_9"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_10"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_11"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_12"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_13"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_14"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/multiplier/result1,result0_sliced_15"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd1"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd2"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/state_FSM_FFd3"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/dc_ss"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_313"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_303"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_293"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_283"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_273"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_263"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_253"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_243"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_233"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_223"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_215"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_203"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_193"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_183"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_173"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_163"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_153"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_143"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_133"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_123"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_115"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_103"
|
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BEL
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|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_93"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_83"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_73"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_63"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_53"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_43"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_34"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_214"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_114"
|
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BEL
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_03"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_312"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_302"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_292"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_282"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_272"
|
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BEL
|
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"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_262"
|
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BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_252"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_242"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_232"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_222"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_213"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_202"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_192"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_182"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_172"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_162"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_152"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_142"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_132"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_122"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_113"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_102"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_92"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_82"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_72"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_62"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_52"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_42"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_33"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_212"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_112"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_02"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_311"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_301"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_291"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_281"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_271"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_261"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_251"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_241"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_231"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_221"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_211"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_201"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_191"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_181"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_171"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_161"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_151"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_141"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_131"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_121"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_111"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_101"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_91"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_81"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_71"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_61"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_51"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_41"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_32"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_210"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_110"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_01"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_31"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_30"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_29"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_28"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_27"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_26"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_25"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_24"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_23"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_22"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_21"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_20"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_19"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_18"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_17"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_16"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_15"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_14"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_13"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_12"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_11"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_10"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_9"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_8"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_7"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_6"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_5"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wp_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/dc_re"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<3>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<2>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<3>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<2>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<1>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<1>_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<0>_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/wpc_c<0>_1"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc2_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc0_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc1_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/iack_o" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_0" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_1" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_2" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_3" BEL
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/inst_LPM_FF_4" BEL
|
|
"u0/u1/crossbar/matrix_old_0_3" BEL "u0/u1/crossbar/matrix_old_0_2"
|
|
BEL "u0/u1/crossbar/matrix_old_0_1" BEL
|
|
"u0/u1/crossbar/matrix_old_0_0" BEL "u0/u1/crossbar/matrix_old_1_3"
|
|
BEL "u0/u1/crossbar/matrix_old_1_2" BEL
|
|
"u0/u1/crossbar/matrix_old_1_1" BEL "u0/u1/crossbar/matrix_old_1_0"
|
|
BEL "u0/u1/rom/adr_reg_5" BEL "u0/u1/rom/adr_reg_4" BEL
|
|
"u0/u1/rom/adr_reg_3" BEL "u0/u1/rom/adr_reg_2" BEL
|
|
"u0/u1/rom/adr_reg_1" BEL "u0/u1/rom/adr_reg_0" BEL
|
|
"u0/u9/crossbar/matrix_old_0_17" BEL "u0/u9/crossbar/matrix_old_0_16"
|
|
BEL "u0/u9/crossbar/matrix_old_0_15" BEL
|
|
"u0/u9/crossbar/matrix_old_0_14" BEL "u0/u9/crossbar/matrix_old_0_13"
|
|
BEL "u0/u9/crossbar/matrix_old_0_12" BEL
|
|
"u0/u9/crossbar/matrix_old_0_11" BEL "u0/u9/crossbar/matrix_old_0_10"
|
|
BEL "u0/u9/crossbar/matrix_old_0_9" BEL
|
|
"u0/u9/crossbar/matrix_old_0_8" BEL "u0/u9/crossbar/matrix_old_0_7"
|
|
BEL "u0/u9/crossbar/matrix_old_0_6" BEL
|
|
"u0/u9/crossbar/matrix_old_0_5" BEL "u0/u9/crossbar/matrix_old_0_4"
|
|
BEL "u0/u9/crossbar/matrix_old_0_3" BEL
|
|
"u0/u9/crossbar/matrix_old_0_2" BEL "u0/u9/crossbar/matrix_old_0_1"
|
|
BEL "u0/u9/crossbar/matrix_old_0_0" BEL "u0/u9/crossbar/virtual_ERR"
|
|
BEL "u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_7" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_6" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_5" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_4" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_3" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_2" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_1" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_rdr_rx_data_i_0" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_16" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_15" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_14" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_13" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_12" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_11" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_10" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_9" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_8" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_7" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_6" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_5" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_4" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_3" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_2" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_1" BEL
|
|
"u0/u12/U_Wrapped_UART/uart_bcr_0" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/rddata_reg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/ack_sreg" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud_sreg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_16"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_15"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_14"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_13"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_12"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_11"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_10"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_9"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_8"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_7"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_6"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_5"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_4"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_3"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_2"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_1"
|
|
BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_BAUD_GEN/Baud8GeneratorAcc_0"
|
|
BEL "u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/state_FSM_FFd3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/TxD_dataReg_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_cnt_inv_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_cnt_inv_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/state_FSM_FFd4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/bit_spacing_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_sync_inv_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_sync_inv_0" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_7" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_6" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_5" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_4" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_3" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_2" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_1" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_0" BEL
|
|
"u0/u3/U_Tics/cntr_tics_31" BEL "u0/u3/U_Tics/cntr_tics_30" BEL
|
|
"u0/u3/U_Tics/cntr_tics_29" BEL "u0/u3/U_Tics/cntr_tics_28" BEL
|
|
"u0/u3/U_Tics/cntr_tics_27" BEL "u0/u3/U_Tics/cntr_tics_26" BEL
|
|
"u0/u3/U_Tics/cntr_tics_25" BEL "u0/u3/U_Tics/cntr_tics_24" BEL
|
|
"u0/u3/U_Tics/cntr_tics_23" BEL "u0/u3/U_Tics/cntr_tics_22" BEL
|
|
"u0/u3/U_Tics/cntr_tics_21" BEL "u0/u3/U_Tics/cntr_tics_20" BEL
|
|
"u0/u3/U_Tics/cntr_tics_19" BEL "u0/u3/U_Tics/cntr_tics_18" BEL
|
|
"u0/u3/U_Tics/cntr_tics_17" BEL "u0/u3/U_Tics/cntr_tics_16" BEL
|
|
"u0/u3/U_Tics/cntr_tics_15" BEL "u0/u3/U_Tics/cntr_tics_14" BEL
|
|
"u0/u3/U_Tics/cntr_tics_13" BEL "u0/u3/U_Tics/cntr_tics_12" BEL
|
|
"u0/u3/U_Tics/cntr_tics_11" BEL "u0/u3/U_Tics/cntr_tics_10" BEL
|
|
"u0/u3/U_Tics/cntr_tics_9" BEL "u0/u3/U_Tics/cntr_tics_8" BEL
|
|
"u0/u3/U_Tics/cntr_tics_7" BEL "u0/u3/U_Tics/cntr_tics_6" BEL
|
|
"u0/u3/U_Tics/cntr_tics_5" BEL "u0/u3/U_Tics/cntr_tics_4" BEL
|
|
"u0/u3/U_Tics/cntr_tics_3" BEL "u0/u3/U_Tics/cntr_tics_2" BEL
|
|
"u0/u3/U_Tics/cntr_tics_1" BEL "u0/u3/U_Tics/cntr_tics_0" BEL
|
|
"u0/u3/U_Tics/cntr_div_23" BEL "u0/u3/U_Tics/cntr_div_22" BEL
|
|
"u0/u3/U_Tics/cntr_div_21" BEL "u0/u3/U_Tics/cntr_div_20" BEL
|
|
"u0/u3/U_Tics/cntr_div_19" BEL "u0/u3/U_Tics/cntr_div_18" BEL
|
|
"u0/u3/U_Tics/cntr_div_17" BEL "u0/u3/U_Tics/cntr_div_16" BEL
|
|
"u0/u3/U_Tics/cntr_div_15" BEL "u0/u3/U_Tics/cntr_div_14" BEL
|
|
"u0/u3/U_Tics/cntr_div_13" BEL "u0/u3/U_Tics/cntr_div_12" BEL
|
|
"u0/u3/U_Tics/cntr_div_11" BEL "u0/u3/U_Tics/cntr_div_10" BEL
|
|
"u0/u3/U_Tics/cntr_div_9" BEL "u0/u3/U_Tics/cntr_div_8" BEL
|
|
"u0/u3/U_Tics/cntr_div_7" BEL "u0/u3/U_Tics/cntr_div_6" BEL
|
|
"u0/u3/U_Tics/cntr_div_5" BEL "u0/u3/U_Tics/cntr_div_4" BEL
|
|
"u0/u3/U_Tics/cntr_div_3" BEL "u0/u3/U_Tics/cntr_div_2" BEL
|
|
"u0/u3/U_Tics/cntr_div_1" BEL "u0/u3/U_Tics/cntr_div_0" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_31" BEL "u0/u3/U_Tics/wb_out_dat_30" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_29" BEL "u0/u3/U_Tics/wb_out_dat_28" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_27" BEL "u0/u3/U_Tics/wb_out_dat_26" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_25" BEL "u0/u3/U_Tics/wb_out_dat_24" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_23" BEL "u0/u3/U_Tics/wb_out_dat_22" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_21" BEL "u0/u3/U_Tics/wb_out_dat_20" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_19" BEL "u0/u3/U_Tics/wb_out_dat_18" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_17" BEL "u0/u3/U_Tics/wb_out_dat_16" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_15" BEL "u0/u3/U_Tics/wb_out_dat_14" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_13" BEL "u0/u3/U_Tics/wb_out_dat_12" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_11" BEL "u0/u3/U_Tics/wb_out_dat_10" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_9" BEL "u0/u3/U_Tics/wb_out_dat_8" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_7" BEL "u0/u3/U_Tics/wb_out_dat_6" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_5" BEL "u0/u3/U_Tics/wb_out_dat_4" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_3" BEL "u0/u3/U_Tics/wb_out_dat_2" BEL
|
|
"u0/u3/U_Tics/wb_out_dat_1" BEL "u0/u3/U_Tics/wb_out_dat_0" BEL
|
|
"u0/u3/U_Tics/cntr_overflow" BEL "u0/u5/Wrapped_GPIO/wb_out_dat_31"
|
|
BEL "u0/u5/Wrapped_GPIO/wb_out_dat_30" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_29" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_28" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_27" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_26" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_25" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_24" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_23" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_22" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_21" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_20" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_19" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_18" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_17" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_16" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_15" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_14" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_13" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_12" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_11" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_10" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_9" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_8" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_7" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_6" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_5" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_4" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_3" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_2" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_1" BEL
|
|
"u0/u5/Wrapped_GPIO/wb_out_dat_0" BEL "u0/u5/Wrapped_GPIO/dir_reg_31"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_30" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_29" BEL "u0/u5/Wrapped_GPIO/dir_reg_28"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_27" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_26" BEL "u0/u5/Wrapped_GPIO/dir_reg_25"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_24" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_23" BEL "u0/u5/Wrapped_GPIO/dir_reg_22"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_21" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_20" BEL "u0/u5/Wrapped_GPIO/dir_reg_19"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_18" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_17" BEL "u0/u5/Wrapped_GPIO/dir_reg_16"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_15" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_14" BEL "u0/u5/Wrapped_GPIO/dir_reg_13"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_12" BEL
|
|
"u0/u5/Wrapped_GPIO/dir_reg_11" BEL "u0/u5/Wrapped_GPIO/dir_reg_10"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_9" BEL "u0/u5/Wrapped_GPIO/dir_reg_8"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_7" BEL "u0/u5/Wrapped_GPIO/dir_reg_6"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_5" BEL "u0/u5/Wrapped_GPIO/dir_reg_4"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_3" BEL "u0/u5/Wrapped_GPIO/dir_reg_2"
|
|
BEL "u0/u5/Wrapped_GPIO/dir_reg_1" BEL "u0/u5/Wrapped_GPIO/dir_reg_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/rxack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_15" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_14" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_13" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_12" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_11" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_10" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_9" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_8" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/prer_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/cr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/ctr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/txr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/irq_flag" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/al" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/tip" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/iack_o" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_dat_o_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/rxack" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_15" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_14" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_13" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_12" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_11" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_10" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_9" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_8" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/prer_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/cr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/ctr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/txr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/irq_flag" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/al" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/tip" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/iack_o" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/shift" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_txd" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ld" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/host_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/c_state_FSM_FFd3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/shift" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_txd" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/sr_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ld" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/core_cmd_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/host_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_15" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_14" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_13" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_12" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_11" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_10" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_9" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_8" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_7" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_6" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_5" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_4" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_3" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_2" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_1" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_0" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd3"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd4"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd5"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cmd_ack" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/ial" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dscl_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_0"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSDA" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSCL" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_13"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_12"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_11"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_10"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_9"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_8"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_7"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_6"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_5"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_4"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_3"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_2"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSDA" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSCL" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sto_condition"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.ibusy"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_1"
|
|
BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_0"
|
|
BEL "u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/clk_en" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_15" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_14" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_13" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_12" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_11" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_10" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_9" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_8" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_7" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_6" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_5" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_4" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_3" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_2" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_1" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cnt_0" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd3"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd4"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/c_state_FSM_FFd5"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/cmd_ack" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/ial" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dscl_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSDA_0"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.fSCL_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSDA" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dSCL" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_13"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_12"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_11"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_10"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_9"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_8"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_7"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_6"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_5"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_4"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_3"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_2"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.filter_cnt_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSDA" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sSCL" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sto_condition"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.ibusy"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSDA_0"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_1"
|
|
BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cSCL_0"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/clk_en" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/slave_wait" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_31" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_30" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_29" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_28" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_27" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_26" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_25" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_24" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_23" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_22" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_21" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_20" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_19" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_18" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_17" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_16" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_dat_o_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/divider_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ss_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_ack_o" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/cnt_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/neg_edge" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/pos_edge" BEL
|
|
"u0/u15/Wrapped_date_rev_id/ack_int" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_enable_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_4"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_3"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_2"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/write_idx_m_0"
|
|
BEL "u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/use_buf"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reset"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_break"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/jtag_access"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cyc_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/stall_wb_load"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_we_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_stb_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_select_m"
|
|
BEL "u0/u14/U_Wrapped_I2C/U_Adapter/fsm_state" BEL
|
|
"u0/u7/U_Wrapped_I2C/U_Adapter/fsm_state" BEL
|
|
"u0/u11/U_Wrapped_tdc/U_Adapter/fsm_state" BEL
|
|
"u0/u12/U_Wrapped_UART/U_Adapter/fsm_state" BEL
|
|
"u0/u12/U_Wrapped_UART/regs_in_sr_rx_rdy_i" BEL
|
|
"u0/u3/U_Tics/U_Adapter/fsm_state" BEL
|
|
"u0/u5/Wrapped_GPIO/U_Adapter/fsm_state" BEL
|
|
"u0/u5/Wrapped_GPIO/ack_int" BEL
|
|
"u0/u18/U_Wrapped_SPI/U_Adapter/fsm_state" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/eie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/ie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/interrupt_unit/bie"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_write_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_csr_write_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/processing"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_read_enable"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cti_o_0"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_we_o"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_load_complete"
|
|
BEL "u0/u12/U_Wrapped_UART/U_WB_SLAVE/rdr_rack_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_host_tdr_data_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_tdr_tx_data_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/U_WB_SLAVE/regs_o_bcr_wr_o" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_bit_inv" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ack_out" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/ack_out" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sda_chk" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dout" BEL
|
|
"u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop"
|
|
BEL "u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/sda_chk" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/dout" BEL
|
|
"u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop"
|
|
BEL "u0/u18/U_Wrapped_SPI/Wrapped_SPI/ctrl_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_0" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_1" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_2" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_3" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_4" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_5" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_6" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_8" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_9" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_7" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_10" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_11" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_12" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_13" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_14" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_15" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_16" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_17" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_18" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_19" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_20" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_21" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_22" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_23" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_25" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_26" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_24" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_27" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_28" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_29" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_30" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_31" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_32" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_33" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_34" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_35" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_36" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_37" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_38" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_39" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_40" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_42" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_43" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_41" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_44" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_45" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_46" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_47" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_48" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_49" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_51" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_52" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_50" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_53" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_54" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_55" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_56" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_57" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_58" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_60" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_61" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_59" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_62" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_63" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_64" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_65" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_66" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_67" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_68" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_69" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_70" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_71" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_72" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_73" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_74" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_75" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_77" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_78" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_76" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_79" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_80" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_81" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_82" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_83" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_84" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_85" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_86" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_87" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_88" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_89" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_90" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_91" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_92" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_94" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_95" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_93" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_96" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_97" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_98" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_99" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_100" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_101" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_102" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_103" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_104" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_105" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_106" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_107" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_108" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_109" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_111" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_112" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_110" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_113" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_114" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_115" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_116" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_117" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_118" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_120" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_121" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_119" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_122" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_123" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_124" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_125" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_126" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/data_127" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/shift/tip" BEL
|
|
"u0/u18/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_f" BEL
|
|
"u7/u1/O_n" BEL "u0/u9/rom/slave_o_ack" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_w" BEL
|
|
"u0/u14/U_Wrapped_I2C/U_Adapter/stored_we" BEL
|
|
"u0/u7/U_Wrapped_I2C/U_Adapter/stored_we" BEL
|
|
"u0/u11/U_Wrapped_tdc/U_Adapter/stored_we" BEL "u0/u4/slave1_out_ack"
|
|
BEL "u0/u1/crossbar/virtual_ERR" BEL "u0/u1/rom/slave_o_ack" BEL
|
|
"u0/u12/U_Wrapped_UART/U_Adapter/stored_we" BEL
|
|
"u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_ready" BEL
|
|
"u0/u3/U_Tics/U_Adapter/stored_we" BEL "u0/u3/U_Tics/wb_out_ack" BEL
|
|
"u0/u5/Wrapped_GPIO/U_Adapter/stored_we" BEL
|
|
"u0/u18/U_Wrapped_SPI/U_Adapter/stored_we" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_x" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_d" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/valid_m" BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_mul_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_m"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_cyc_o_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/exception_m_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/state_FSM_FFd2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_3_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_2_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_0_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_1_1"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4_1"
|
|
BEL "u8/u1/Mshreg_O" BEL "u8/u1/O" BEL "u6/u1/Mshreg_O" BEL "u6/u1/O"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem_pins<33>"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram_pins<33>"
|
|
BEL
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram_pins<33>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<63>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<62>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<65>"
|
|
PIN
|
|
"u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/Mram_mem_pins<64>"
|
|
PIN "u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8_pins<64>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<63>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<62>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<65>" PIN
|
|
"u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9_pins<64>" PIN
|
|
"u0_u9/rom/Mram_rom_pins<63>" PIN "u0_u9/rom/Mram_rom_pins<62>" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst_pins<2>";
|
|
PIN u1/mmcm_adv_inst_pins<2> = BEL "u1/mmcm_adv_inst" PINNAME CLKIN1;
|
|
TIMEGRP ClkI_p = BEL "u5" BEL "u1/clkin1_buf" PIN "u1/mmcm_adv_inst_pins<2>";
|
|
TIMEGRP ClkI_n = BEL "u5" BEL "u1/clkin1_buf" PIN "u1/mmcm_adv_inst_pins<2>";
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<3>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master"
|
|
PINNAME CLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<4>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master"
|
|
PINNAME CLKB;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<3>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master"
|
|
PINNAME CLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<4>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master"
|
|
PINNAME CLKB;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PINNAME CLKBWRCLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PINNAME CLKBWRCLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKARDCLKU;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKARDCLKL;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKBWRCLKU;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKBWRCLKL;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKARDCLKU;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKARDCLKL;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKBWRCLKU;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"
|
|
PINNAME CLKBWRCLKL;
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout1_buf" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_state_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_state_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_ts_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/new_time_slice" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/index_ch_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/index_ch_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/ts_complete_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/ts_complete_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_0"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_en" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<4>"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/p_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/p_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_39"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_38"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_37"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_36"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_35"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_34"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_33"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_32"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/enable_ts"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/p_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/p_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_39"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_38"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_37"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_36"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_35"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_34"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_33"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_32"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/enable_ts"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_word_end" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_en" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/enable_download" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_ready" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/flag_rem"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/flag_rem"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_end" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/n_d"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/n_d"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>";
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0_0 = BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout1_buf" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_state_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_state_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_ts_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/new_time_slice" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/index_ch_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/index_ch_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/ts_complete_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/ts_complete_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_31" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_30" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_29" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_28" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_27" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_26" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_25" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_24" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_23" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_22" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_21" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_20" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_19" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_18" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_17" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_16" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_15" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_14" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_13" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_12" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_11" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_10" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_9" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_8" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_7" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_6" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_bytes_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_5" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_4" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_gen.counter_0"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd3" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_fsm_FSM_FFd1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_2" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_1" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_cnt_0" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_clk_en" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<4>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<3>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<4>"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/p_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/p_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_39"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_38"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_37"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_36"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_35"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_34"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_33"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_32"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/d_out_ts_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_rem_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/count_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/enable_ts"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/p_state_FSM_FFd2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/p_state_FSM_FFd1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_39"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_38"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_37"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_36"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_35"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_34"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_33"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_32"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/d_out_ts_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_ts_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_31"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_30"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_29"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_28"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_27"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_26"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_25"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_24"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_23"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_22"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_21"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_20"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_19"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_18"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_17"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_16"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_15"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_14"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_13"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_12"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_11"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_10"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_rem_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/count_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/enable_ts"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_word_end" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_en" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/enable_download" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_ready" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/flag_rem"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/flag_rem"
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_end" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/n_d"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/n_d"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_9"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_8"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_7"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_5"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_4"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_3"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_2"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_0"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>"
|
|
BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram_pins<33>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>";
|
|
PIN u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst_pins<2> =
|
|
BEL "u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst"
|
|
PINNAME CLKIN1;
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst_pins<2>";
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0_0 = BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf" PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst_pins<2>";
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<8>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master"
|
|
PINNAME OCLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<9>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master"
|
|
PINNAME OCLKB;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<8>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master"
|
|
PINNAME OCLK;
|
|
PIN
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<9>
|
|
= BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master"
|
|
PINNAME OCLKB;
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<9>"
|
|
BEL "s_o" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf";
|
|
TIMEGRP u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1_0 = PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<9>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<8>"
|
|
PIN
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/iserdes_master_pins<9>"
|
|
BEL "s_o" BEL
|
|
"u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf";
|
|
TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;
|
|
TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0"
|
|
TS_u1_clkout0 / 4 HIGH 50%;
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1
|
|
ns HIGH 50%;
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;
|
|
SCHEMATIC END;
|
|
|