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4222 lines
381 KiB
Plaintext
4222 lines
381 KiB
Plaintext
Release 14.2 - xst P.28xd (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.34 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.36 secs
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--> Reading design: fpga.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "fpga.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "fpga"
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Output Format : NGC
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Target Device : xc7k325t-2-ffg900
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---- Source Options
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Top Module Name : fpga
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 32
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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---- Other Options
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Cores Search Directories : {"../../ip_cores" }
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_shift.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/spi_defines.v" included at line 41.
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/timescale.v" included at line 42.
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Parsing module <spi_shift>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_clgen.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/spi_defines.v" included at line 41.
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/timescale.v" included at line 42.
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Parsing module <spi_clgen>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_addsub.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\/lm32_include.v" included at line 28.
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Parsing module <lm32_addsub>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\platform\kintex7\jtag_tap.v" into library work
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Parsing module <jtag_tap>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_top.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/spi_defines.v" included at line 42.
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\/timescale.v" included at line 43.
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Parsing module <spi_top>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_shifter.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\/lm32_include.v" included at line 29.
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Parsing module <lm32_shifter>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_ram.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\/lm32_include.v" included at line 34.
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Parsing module <lm32_ram>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_logic_op.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\/lm32_include.v" included at line 29.
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Parsing module <lm32_logic_op>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_dp_ram.v" into library work
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Parsing module <lm32_dp_ram>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_adder.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\/lm32_include.v" included at line 29.
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Parsing module <lm32_adder>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\jtag_cores.v" into library work
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Parsing module <jtag_cores>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\platform\kintex7\lm32_multiplier.v" into library work
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Parsing verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\platform\kintex7\/../../src/lm32_include.v" included at line 29.
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Parsing module <lm32_multiplier>.
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Analyzing Verilog file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" into library work
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Parsing module <lm32_top_full_debug>.
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Parsing module <lm32_mc_arithmetic_full_debug>.
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Parsing module <lm32_cpu_full_debug>.
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Parsing module <lm32_load_store_unit_full_debug>.
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Parsing module <lm32_decoder_full_debug>.
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Parsing module <lm32_icache_full_debug>.
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Parsing module <lm32_dcache_full_debug>.
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Parsing module <lm32_debug_full_debug>.
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Parsing module <lm32_instruction_unit_full_debug>.
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Parsing module <lm32_jtag_full_debug>.
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Parsing module <lm32_interrupt_full_debug>.
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Parsing module <lm32_top_full>.
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Parsing module <lm32_mc_arithmetic_full>.
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Parsing module <lm32_cpu_full>.
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Parsing module <lm32_load_store_unit_full>.
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Parsing module <lm32_decoder_full>.
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Parsing module <lm32_icache_full>.
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Parsing module <lm32_dcache_full>.
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Parsing module <lm32_instruction_unit_full>.
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Parsing module <lm32_interrupt_full>.
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Parsing module <lm32_top_medium_debug>.
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Parsing module <lm32_mc_arithmetic_medium_debug>.
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Parsing module <lm32_cpu_medium_debug>.
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Parsing module <lm32_load_store_unit_medium_debug>.
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Parsing module <lm32_decoder_medium_debug>.
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Parsing module <lm32_icache_medium_debug>.
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Parsing module <lm32_debug_medium_debug>.
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Parsing module <lm32_instruction_unit_medium_debug>.
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Parsing module <lm32_jtag_medium_debug>.
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Parsing module <lm32_interrupt_medium_debug>.
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Parsing module <lm32_top_medium_icache_debug>.
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Parsing module <lm32_mc_arithmetic_medium_icache_debug>.
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Parsing module <lm32_cpu_medium_icache_debug>.
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Parsing module <lm32_load_store_unit_medium_icache_debug>.
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Parsing module <lm32_decoder_medium_icache_debug>.
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Parsing module <lm32_icache_medium_icache_debug>.
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Parsing module <lm32_debug_medium_icache_debug>.
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Parsing module <lm32_instruction_unit_medium_icache_debug>.
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Parsing module <lm32_jtag_medium_icache_debug>.
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Parsing module <lm32_interrupt_medium_icache_debug>.
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Parsing module <lm32_top_medium_icache>.
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Parsing module <lm32_mc_arithmetic_medium_icache>.
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Parsing module <lm32_cpu_medium_icache>.
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Parsing module <lm32_load_store_unit_medium_icache>.
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Parsing module <lm32_decoder_medium_icache>.
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Parsing module <lm32_icache_medium_icache>.
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Parsing module <lm32_instruction_unit_medium_icache>.
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Parsing module <lm32_interrupt_medium_icache>.
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Parsing module <lm32_top_medium>.
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Parsing module <lm32_mc_arithmetic_medium>.
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Parsing module <lm32_cpu_medium>.
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Parsing module <lm32_load_store_unit_medium>.
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Parsing module <lm32_decoder_medium>.
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Parsing module <lm32_instruction_unit_medium>.
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Parsing module <lm32_interrupt_medium>.
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Parsing module <lm32_top_minimal>.
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Parsing module <lm32_mc_arithmetic_minimal>.
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Parsing module <lm32_cpu_minimal>.
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Parsing module <lm32_load_store_unit_minimal>.
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Parsing module <lm32_decoder_minimal>.
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Parsing module <lm32_instruction_unit_minimal>.
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Parsing module <lm32_interrupt_minimal>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\ip_cores\fifo_synth.vhd" into library work
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Parsing entity <fifo>.
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Parsing architecture <kintex7> of entity <fifo>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\ip_cores\fifo.vhd" into library work
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Parsing entity <fifo>.
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Parsing architecture <fifo_a> of entity <fifo>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\DRU.vhd" into library work
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Parsing entity <DRU>.
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Parsing architecture <Behavioral> of entity <dru>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_bit_ctrl.vhd" into library work
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Parsing entity <i2c_master_bit_ctrl>.
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Parsing architecture <structural> of entity <i2c_master_bit_ctrl>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\genram_pkg.vhd" into library work
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Parsing package <genram_pkg>.
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Parsing package body <genram_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\uart232.vhd" into library work
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Parsing entity <uart>.
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Parsing architecture <Behavioral> of entity <uart>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" into library work
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Parsing entity <tdc_top>.
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Parsing architecture <Behavioral> of entity <tdc_top>.
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WARNING:HDLCompiler:946 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 258: Actual for formal port clkb is neither a static name nor a globally static expression
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WARNING:HDLCompiler:946 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 260: Actual for formal port oclkb is neither a static name nor a globally static expression
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mydcm_phases.vhd" into library work
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Parsing entity <mydcm_phases>.
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Parsing architecture <xilinx> of entity <mydcm_phases>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\dcm_tdc_250.vhd" into library work
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Parsing entity <dcm_tdc_250>.
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Parsing architecture <xilinx> of entity <dcm_tdc_250>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd" into library work
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Parsing package <wishbone_pkg>.
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Parsing package body <wishbone_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_pkg.vhd" into library work
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Parsing package <uart_wbgen2_pkg>.
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Parsing package body <uart_wbgen2_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_byte_ctrl.vhd" into library work
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Parsing entity <i2c_master_byte_ctrl>.
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Parsing architecture <structural> of entity <i2c_master_byte_ctrl>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\memory_loader_pkg.vhd" into library work
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Parsing package <memory_loader_pkg>.
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Parsing package body <memory_loader_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot.vhd" into library work
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Parsing entity <multiboot>.
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Parsing architecture <Behavioral> of entity <multiboot>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" into library work
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Parsing entity <mux_tdc>.
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Parsing architecture <Behavioral> of entity <mux_tdc>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\tdc_pkg.vhd" into library work
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Parsing package <tdc_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\modules\fabric\wr_fabric_pkg.vhd" into library work
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Parsing package <wr_fabric_pkg>.
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Parsing package body <wr_fabric_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_baud_gen.vhd" into library work
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Parsing entity <uart_baud_gen>.
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Parsing architecture <behavioral> of entity <uart_baud_gen>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_async_tx.vhd" into library work
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Parsing entity <uart_async_tx>.
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Parsing architecture <behavioral> of entity <uart_async_tx>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_async_rx.vhd" into library work
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Parsing entity <uart_async_rx>.
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Parsing architecture <behavioral> of entity <uart_async_rx>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" into library work
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Parsing entity <simple_uart_wb>.
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Parsing architecture <syn> of entity <simple_uart_wb>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_top.vhd" into library work
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Parsing entity <i2c_master_top>.
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Parsing architecture <structural> of entity <i2c_master_top>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd" into library work
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Parsing entity <generic_dpram_sameclock>.
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Parsing architecture <syn> of entity <generic_dpram_sameclock>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_dualclock.vhd" into library work
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Parsing entity <generic_dpram_dualclock>.
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Parsing architecture <syn> of entity <generic_dpram_dualclock>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\common\gencores_pkg.vhd" into library work
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Parsing package <gencores_pkg>.
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Parsing package body <gencores_pkg>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\common\gc_sync_ffs.vhd" into library work
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Parsing entity <gc_sync_ffs>.
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Parsing architecture <behavioral> of entity <gc_sync_ffs>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot_master_top.vhd" into library work
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Parsing entity <multiboot_master_top>.
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Parsing architecture <structural> of entity <multiboot_master_top>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wrapped_mux_tdc.vhd" into library work
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Parsing entity <tdc_master_top>.
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Parsing architecture <structural> of entity <tdc_master_top>.
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Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd" into library work
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Parsing entity <wb_slave_adapter>.
|
|
Parsing architecture <rtl> of entity <wb_slave_adapter>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\modules\wr_endpoint\endpoint_pkg.vhd" into library work
|
|
Parsing package <endpoint_pkg>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\modules\wrc_core\wrc_syscon_pkg.vhd" into library work
|
|
Parsing package <sysc_wbgen2_pkg>.
|
|
Parsing package body <sysc_wbgen2_pkg>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" into library work
|
|
Parsing entity <wb_simple_uart>.
|
|
Parsing architecture <syn> of entity <wb_simple_uart>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" into library work
|
|
Parsing entity <wb_spi>.
|
|
Parsing architecture <rtl> of entity <wb_spi>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" into library work
|
|
Parsing entity <wb_tics>.
|
|
Parsing architecture <behaviour> of entity <wb_tics>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" into library work
|
|
Parsing entity <wb_i2c_master>.
|
|
Parsing architecture <rtl> of entity <wb_i2c_master>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" into library work
|
|
Parsing entity <wb_gpio_port>.
|
|
Parsing architecture <behavioral> of entity <wb_gpio_port>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_crossbar.vhd" into library work
|
|
Parsing entity <xwb_crossbar>.
|
|
Parsing architecture <rtl> of entity <xwb_crossbar>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\sdb_rom.vhd" into library work
|
|
Parsing entity <sdb_rom>.
|
|
Parsing architecture <rtl> of entity <sdb_rom>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram.vhd" into library work
|
|
Parsing entity <generic_dpram>.
|
|
Parsing architecture <syn> of entity <generic_dpram>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" into library work
|
|
Parsing entity <wb_multiboot>.
|
|
Parsing architecture <rtl> of entity <wb_multiboot>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" into library work
|
|
Parsing entity <wb_tdc_master>.
|
|
Parsing architecture <rtl> of entity <wb_tdc_master>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" into library work
|
|
Parsing entity <wb_date_rev_id>.
|
|
Parsing architecture <behavioral> of entity <wb_date_rev_id>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\aes_pkg.vhd" into library work
|
|
Parsing package <aes_pkg>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\modules\wrc_core\wrcore_pkg.vhd" into library work
|
|
Parsing package <wrcore_pkg>.
|
|
Parsing package body <wrcore_pkg>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\xwb_simple_uart.vhd" into library work
|
|
Parsing entity <xwb_simple_uart>.
|
|
Parsing architecture <rtl> of entity <xwb_simple_uart>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\xwb_spi.vhd" into library work
|
|
Parsing entity <xwb_spi>.
|
|
Parsing architecture <rtl> of entity <xwb_spi>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\xwb_tics.vhd" into library work
|
|
Parsing entity <xwb_tics>.
|
|
Parsing architecture <rtl> of entity <xwb_tics>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" into library work
|
|
Parsing entity <xwb_lm32>.
|
|
Parsing architecture <rtl> of entity <xwb_lm32>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\xwb_i2c_master.vhd" into library work
|
|
Parsing entity <xwb_i2c_master>.
|
|
Parsing architecture <rtl> of entity <xwb_i2c_master>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\xwb_gpio_port.vhd" into library work
|
|
Parsing entity <xwb_gpio_port>.
|
|
Parsing architecture <rtl> of entity <xwb_gpio_port>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" into library work
|
|
Parsing entity <xwb_dpram>.
|
|
Parsing architecture <struct> of entity <xwb_dpram>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_sdb_crossbar.vhd" into library work
|
|
Parsing entity <xwb_sdb_crossbar>.
|
|
Parsing architecture <rtl> of entity <xwb_sdb_crossbar>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\xwb_multiboot.vhd" into library work
|
|
Parsing entity <xwb_multiboot>.
|
|
Parsing architecture <rtl> of entity <xwb_multiboot>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\xwb_aes_empty.vhd" into library work
|
|
Parsing entity <xwb_aes>.
|
|
Parsing architecture <rtl> of entity <xwb_aes>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\xwb_tdc.vhd" into library work
|
|
Parsing entity <xwb_tdc>.
|
|
Parsing architecture <rtl> of entity <xwb_tdc>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\xwb_date_rev_id.vhd" into library work
|
|
Parsing entity <xwb_date_rev_id>.
|
|
Parsing architecture <rtl> of entity <xwb_date_rev_id>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\lm32_2nd_pkg.vhd" into library work
|
|
Parsing package <lm32_2nd_pkg>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\ip_cores\cmp_sys_clk_pll.vhd" into library work
|
|
Parsing entity <cmp_sys_clk_pll>.
|
|
Parsing architecture <xilinx> of entity <cmp_sys_clk_pll>.
|
|
Parsing VHDL file "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" into library work
|
|
Parsing entity <low>.
|
|
Parsing architecture <structure> of entity <low>.
|
|
Parsing entity <dummy_aes>.
|
|
Parsing architecture <rtl> of entity <dummy_aes>.
|
|
Parsing entity <tri_state>.
|
|
Parsing architecture <structure> of entity <tri_state>.
|
|
Parsing entity <DummySlave>.
|
|
Parsing architecture <a0> of entity <dummyslave>.
|
|
Parsing entity <Dum_mnic>.
|
|
Parsing architecture <a0> of entity <dum_mnic>.
|
|
Parsing entity <lm32_2nd>.
|
|
Parsing architecture <a0> of entity <lm32_2nd>.
|
|
Parsing entity <i_tdc>.
|
|
Parsing architecture <rtl> of entity <i_tdc>.
|
|
Parsing entity <Reg1NoRst>.
|
|
Parsing architecture <rtl> of entity <reg1norst>.
|
|
Parsing entity <MetaStabelizer>.
|
|
Parsing architecture <rtl> of entity <metastabelizer>.
|
|
Parsing entity <Counter>.
|
|
Parsing architecture <rtl> of entity <counter>.
|
|
Parsing entity <fpga>.
|
|
Parsing architecture <a0> of entity <fpga>.
|
|
|
|
=========================================================================
|
|
* HDL Elaboration *
|
|
=========================================================================
|
|
WARNING:HDLCompiler:746 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\genram_pkg.vhd" Line 50: Range is empty (null range)
|
|
|
|
Elaborating entity <fpga> (architecture <a0>) with generics from library <work>.
|
|
|
|
Elaborating entity <Counter> (architecture <rtl>) from library <work>.
|
|
|
|
Elaborating entity <MetaStabelizer> (architecture <rtl>) from library <work>.
|
|
|
|
Elaborating entity <Reg1NoRst> (architecture <rtl>) from library <work>.
|
|
WARNING:HDLCompiler:89 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" Line 1102: <ibufds_gte2> remains a black-box since it has no binding entity.
|
|
WARNING:HDLCompiler:244 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" Line 1116: Binding entity lm32_2nd does not have generic c_tdc_channels
|
|
INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" Line 250. lm32_2nd is declared here
|
|
|
|
Elaborating entity <lm32_2nd> (architecture <a0>) with generics from library <work>.
|
|
|
|
Elaborating entity <Dum_mnic> (architecture <a0>) with generics from library <work>.
|
|
|
|
Elaborating entity <DummySlave> (architecture <a0>) from library <work>.
|
|
|
|
Elaborating entity <xwb_lm32> (architecture <rtl>) with generics from library <work>.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE.
|
|
Going to verilog side to elaborate module lm32_top_medium_icache_debug
|
|
|
|
Elaborating module <lm32_top_medium_icache_debug>.
|
|
|
|
Elaborating module <lm32_cpu_medium_icache_debug>.
|
|
|
|
Elaborating module <lm32_instruction_unit_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
|
|
|
|
Elaborating module <lm32_icache_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.
|
|
|
|
Elaborating module <lm32_ram(data_width=32,address_width=32'sb01010)>.
|
|
|
|
Elaborating module <lm32_ram(data_width=32'sb010100,address_width=32'sb01000)>.
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 49062: Result of 30-bit expression is truncated to fit in 29-bit target.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 41112: Assignment to pc_w ignored, since the identifier is never used
|
|
|
|
Elaborating module <lm32_decoder_medium_icache_debug>.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 45384: Assignment to op_user ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 45418: Assignment to multiply ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 45628: Result of 32-bit expression is truncated to fit in 29-bit target.
|
|
|
|
Elaborating module <lm32_load_store_unit_medium_icache_debug(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)>.
|
|
"C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 44391. $display Data bus error. Address: 0
|
|
"C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 44539. $display Warning: Non-aligned halfword access. Address: 0x0 Time: $time .
|
|
"C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 44541. $display Warning: Non-aligned word access. Address: 0x0 Time: $time .
|
|
|
|
Elaborating module <lm32_adder>.
|
|
|
|
Elaborating module <lm32_addsub>.
|
|
|
|
Elaborating module <lm32_logic_op>.
|
|
|
|
Elaborating module <lm32_shifter>.
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_shifter.v" Line 128: Result of 64-bit expression is truncated to fit in 32-bit target.
|
|
|
|
Elaborating module <lm32_multiplier>.
|
|
|
|
Elaborating module <lm32_interrupt_medium_icache_debug>.
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50713: Result of 3-bit expression is truncated to fit in 1-bit target.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50713: Assignment to ie_csr_read_data ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50724: Result of 32-bit expression is truncated to fit in 1-bit target.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50724: Assignment to ip_csr_read_data ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:413 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50725: Result of 32-bit expression is truncated to fit in 1-bit target.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 50725: Assignment to im_csr_read_data ignored, since the identifier is never used
|
|
|
|
Elaborating module <lm32_jtag_medium_icache_debug>.
|
|
|
|
Elaborating module <lm32_debug_medium_icache_debug(breakpoints=0,watchpoints=32'b0100)>.
|
|
|
|
Elaborating module <lm32_dp_ram(addr_depth=32'sb0100000,addr_width=5,data_width=32)>.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 42757: Assignment to x_result_sel_logic_x ignored, since the identifier is never used
|
|
|
|
Elaborating module <jtag_cores>.
|
|
|
|
Elaborating module <jtag_tap>.
|
|
|
|
Elaborating module <BSCANE2(JTAG_CHAIN=1)>.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" Line 39174: Assignment to jrstn ignored, since the identifier is never used
|
|
Back to vhdl to continue elaboration
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE.
|
|
|
|
Elaborating entity <xwb_dpram> (architecture <struct>) with generics from library <work>.
|
|
|
|
Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
|
|
|
|
Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
|
|
|
|
Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.
|
|
|
|
Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
|
|
WARNING:HDLCompiler:321 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE.
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" Line 72: Net <slave1_out_int> does not have a driver.
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" Line 74: Net <slave2_out_int> does not have a driver.
|
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|
Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.
|
|
Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x13fff). This is not supported by the crossbar."
|
|
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|
Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.
|
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Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
|
|
Note: "Mapping slave #0[0x0/0x20000]"
|
|
Note: "Mapping slave #1[0x20000/0x3e000]"
|
|
Note: "Mapping slave #2[0x30000/0x3ff00]"
|
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|
Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.
|
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|
Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.
|
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|
Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
|
|
Note: "Mapping slave #0[0x0/0x1f00]"
|
|
Note: "Mapping slave #1[0x100/0x1f00]"
|
|
Note: "Mapping slave #2[0x200/0x1f00]"
|
|
Note: "Mapping slave #3[0x300/0x1f00]"
|
|
Note: "Mapping slave #4[0x400/0x1f00]"
|
|
Note: "Mapping slave #5[0x500/0x1f00]"
|
|
Note: "Mapping slave #6[0x600/0x1f00]"
|
|
Note: "Mapping slave #7[0x700/0x1f00]"
|
|
Note: "Mapping slave #8[0x800/0x1f00]"
|
|
Note: "Mapping slave #9[0x900/0x1f00]"
|
|
Note: "Mapping slave #10[0xa00/0x1f00]"
|
|
Note: "Mapping slave #11[0xb00/0x1f00]"
|
|
Note: "Mapping slave #12[0xc00/0x1f00]"
|
|
Note: "Mapping slave #13[0xd00/0x1f00]"
|
|
Note: "Mapping slave #14[0xe00/0x1f00]"
|
|
Note: "Mapping slave #15[0xf00/0x1f00]"
|
|
Note: "Mapping slave #16[0x1000/0x1800]"
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Elaborating entity <xwb_simple_uart> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <wb_simple_uart> (architecture <syn>) with generics from library <work>.
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Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
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|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd" Line 186: fsm_state should be on the sensitivity list of the process
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|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd" Line 188: stored_we should be on the sensitivity list of the process
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|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd" Line 194: fsm_state should be on the sensitivity list of the process
|
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Elaborating entity <simple_uart_wb> (architecture <syn>) from library <work>.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used
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|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" Line 58: Assignment to rd_int ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" Line 59: Assignment to wr_int ignored, since the identifier is never used
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|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" Line 60: Assignment to allones ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd" Line 61: Assignment to allzeros ignored, since the identifier is never used
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Elaborating entity <uart_baud_gen> (architecture <behavioral>) with generics from library <work>.
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Elaborating entity <uart_async_tx> (architecture <behavioral>) from library <work>.
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|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected
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Elaborating entity <uart_async_rx> (architecture <behavioral>) from library <work>.
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|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" Line 130: Net <wb_out_err> does not have a driver.
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" Line 132: Net <regs_in_host_tdr_rdy_i> does not have a driver.
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Elaborating entity <xwb_tics> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <wb_tics> (architecture <behaviour>) with generics from library <work>.
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WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" Line 65: Net <wb_out_err> does not have a driver.
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Elaborating entity <xwb_gpio_port> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <wb_gpio_port> (architecture <behavioral>) with generics from library <work>.
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Elaborating entity <gc_sync_ffs> (architecture <behavioral>) with generics from library <work>.
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" Line 78: Net <gpio_in_synced[31]> does not have a driver.
|
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Elaborating entity <xwb_i2c_master> (architecture <rtl>) with generics from library <work>.
|
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Elaborating entity <wb_i2c_master> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <i2c_master_top> (architecture <structural>) with generics from library <work>.
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected
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Elaborating entity <i2c_master_byte_ctrl> (architecture <structural>) from library <work>.
|
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Elaborating entity <i2c_master_bit_ctrl> (architecture <structural>) from library <work>.
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" Line 90: Net <wb_out_err> does not have a driver.
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Elaborating entity <tri_state> (architecture <structure>) from library <work>.
|
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|
Elaborating entity <xwb_date_rev_id> (architecture <rtl>) with generics from library <work>.
|
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Elaborating entity <wb_date_rev_id> (architecture <behavioral>) with generics from library <work>.
|
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Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" Line 120: Assignment to sel ignored, since the identifier is never used
|
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|
Elaborating entity <xwb_spi> (architecture <rtl>) with generics from library <work>.
|
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|
|
Elaborating entity <wb_spi> (architecture <rtl>) with generics from library <work>.
|
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|
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Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
|
|
Going to verilog side to elaborate module spi_top
|
|
|
|
Elaborating module <spi_top(Tp=1)>.
|
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|
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Elaborating module <spi_clgen>.
|
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|
|
Elaborating module <spi_shift>.
|
|
Back to vhdl to continue elaboration
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" Line 61: Net <wb_out_rty> does not have a driver.
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|
Elaborating entity <xwb_tdc> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <wb_tdc_master> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <tdc_master_top> (architecture <structural>) with generics from library <work>.
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|
WARNING:HDLCompiler:439 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wrapped_mux_tdc.vhd" Line 54: Formal port rtdc3 of mode out cannot be associated with actual port rtdc3 of mode in
|
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INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 33. rtdc3 is declared here
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WARNING:HDLCompiler:439 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wrapped_mux_tdc.vhd" Line 55: Formal port rtdc4 of mode out cannot be associated with actual port rtdc4 of mode in
|
|
INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 34. rtdc4 is declared here
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|
Elaborating entity <mux_tdc> (architecture <Behavioral>) with generics from library <work>.
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Elaborating entity <dcm_tdc_250> (architecture <xilinx>) from library <work>.
|
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|
Elaborating entity <mydcm_phases> (architecture <xilinx>) from library <work>.
|
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|
Elaborating entity <uart> (architecture <Behavioral>) with generics from library <work>.
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\uart232.vhd" Line 137. Case statement is complete. others clause is never selected
|
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|
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Elaborating entity <tdc_top> (architecture <Behavioral>) from library <work>.
|
|
WARNING:HDLCompiler:871 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 114: Using initial value '0' for clk_g since it is never assigned
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WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 137: Assignment to clk180 ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 138: Assignment to clk270 ignored, since the identifier is never used
|
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|
Elaborating entity <DRU> (architecture <Behavioral>) from library <work>.
|
|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\DRU.vhd" Line 42: rst should be on the sensitivity list of the process
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\DRU.vhd" Line 41: Assignment to count_ts_next ignored, since the identifier is never used
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|
|
Elaborating entity <fifo> (architecture <fifo_a>) from library <work>.
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|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 234: Assignment to wea ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" Line 119: Net <SYNC_OUT[0]> does not have a driver.
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WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 294: rst should be on the sensitivity list of the process
|
|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 329: rst should be on the sensitivity list of the process
|
|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 340: rst should be on the sensitivity list of the process
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 420. Case statement is complete. others clause is never selected
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 339: Assignment to ts_complete ignored, since the identifier is never used
|
|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 431: rst should be on the sensitivity list of the process
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 486. Case statement is complete. others clause is never selected
|
|
WARNING:HDLCompiler:1127 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 429: Assignment to read_ipmux ignored, since the identifier is never used
|
|
INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 33. rtdc3 is declared here
|
|
INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" Line 34. rtdc4 is declared here
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" Line 72: Net <wb_out_err> does not have a driver.
|
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|
|
Elaborating entity <xwb_multiboot> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <wb_multiboot> (architecture <rtl>) with generics from library <work>.
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|
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Elaborating entity <multiboot_master_top> (architecture <structural>) with generics from library <work>.
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Elaborating entity <multiboot> (architecture <Behavioral>) from library <work>.
|
|
WARNING:HDLCompiler:92 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot.vhd" Line 50: rst should be on the sensitivity list of the process
|
|
INFO:HDLCompiler:679 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot.vhd" Line 123. Case statement is complete. others clause is never selected
|
|
WARNING:HDLCompiler:634 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" Line 65: Net <wb_out_err> does not have a driver.
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Elaborating entity <xwb_aes> (architecture <rtl>) with generics from library <work>.
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|
WARNING:HDLCompiler:244 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" Line 1116: Binding entity lm32_2nd does not have generic c_tdc_channels
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INFO:HDLCompiler:1408 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" Line 250. lm32_2nd is declared here
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Elaborating entity <cmp_sys_clk_pll> (architecture <xilinx>) from library <work>.
|
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|
|
Elaborating entity <dummy_aes> (architecture <rtl>) from library <work>.
|
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|
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Elaborating entity <i_tdc> (architecture <rtl>) with generics from library <work>.
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Elaborating entity <low> (architecture <structure>) with generics from library <work>.
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|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
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|
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Synthesizing Unit <fpga>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
g_date_id = 0
|
|
g_revision_id = 0
|
|
g_dpram_size = 20480
|
|
c_tdc_channels = 3
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1197: Output port <ODIV2> of the instance <u5> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1205: Output port <GPIO_LED> of the instance <u0> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1205: Output port <aes_o_fifo_dout> of the instance <u0> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1205: Output port <aes_o_fifo_full> of the instance <u0> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1205: Output port <aes_o_fifo_empty> of the instance <u0> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1205: Output port <tdc_o_txd> of the instance <u0> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1231: Output port <clk_125_o> of the instance <u1> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1231: Output port <locked_o> of the instance <u1> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1259: Output port <O_n> of the instance <u6> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 1266: Output port <O_n> of the instance <u8> is unconnected or connected to loadless signal.
|
|
Summary:
|
|
no macro.
|
|
Unit <fpga> synthesized.
|
|
|
|
Synthesizing Unit <Counter>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
Found 32-bit register for signal <Count>.
|
|
Found 32-bit adder for signal <Count[31]_GND_15_o_add_0_OUT> created at line 1241.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 32 D-type flip-flop(s).
|
|
Unit <Counter> synthesized.
|
|
|
|
Synthesizing Unit <MetaStabelizer>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 954: Output port <O_n> of the instance <u0> is unconnected or connected to loadless signal.
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Summary:
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no macro.
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Unit <MetaStabelizer> synthesized.
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Synthesizing Unit <Reg1NoRst>.
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Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
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Found 1-bit register for signal <O_n>.
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Found 1-bit register for signal <O>.
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Summary:
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inferred 2 D-type flip-flop(s).
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Unit <Reg1NoRst> synthesized.
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Synthesizing Unit <lm32_2nd>.
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Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
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g_dpram_size = 20480
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g_date_id = 0
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g_revision_id = 0
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_dat> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_ack> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_err> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_rty> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_stall> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 562: Output port <slave_o_int> of the instance <u2> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_dat> of the instance <u1> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_ack> of the instance <u1> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_err> of the instance <u1> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_rty> of the instance <u1> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_stall> of the instance <u1> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 597: Output port <slave_o[2]_int> of the instance <u1> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_adr> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_sel> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_dat> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[15]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[14]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[13]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[12]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[11]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_cyc> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_stb> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 613: Output port <master_o[10]_we> of the instance <u9> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 629: Output port <desc_o> of the instance <u12> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 643: Output port <desc_o> of the instance <u3> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 655: Output port <desc_o> of the instance <u5> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 655: Output port <gpio_oen_o> of the instance <u5> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 672: Output port <desc_o> of the instance <u7> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 701: Output port <desc_o> of the instance <u14> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 742: Output port <desc_o> of the instance <u18> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 757: Output port <desc_o> of the instance <u11> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 771: Output port <desc_o> of the instance <u13> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 785: Output port <desc_o> of the instance <u19> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_adr> of the instance <u20> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_sel> of the instance <u20> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_dat> of the instance <u20> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_cyc> of the instance <u20> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_stb> of the instance <u20> is unconnected or connected to loadless signal.
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INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 801: Output port <slave_i_we> of the instance <u20> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_adr> of the instance <u21> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_sel> of the instance <u21> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_dat> of the instance <u21> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_cyc> of the instance <u21> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_stb> of the instance <u21> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 806: Output port <slave_i_we> of the instance <u21> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_adr> of the instance <u22> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_sel> of the instance <u22> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_dat> of the instance <u22> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_cyc> of the instance <u22> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_stb> of the instance <u22> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 811: Output port <slave_i_we> of the instance <u22> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_adr> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_sel> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_dat> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_cyc> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_stb> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 816: Output port <slave_i_we> of the instance <u23> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_adr> of the instance <u24> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_sel> of the instance <u24> is unconnected or connected to loadless signal.
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|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_dat> of the instance <u24> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_cyc> of the instance <u24> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_stb> of the instance <u24> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 821: Output port <slave_i_we> of the instance <u24> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_adr> of the instance <u25> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_sel> of the instance <u25> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_dat> of the instance <u25> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_cyc> of the instance <u25> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_stb> of the instance <u25> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd" line 826: Output port <slave_i_we> of the instance <u25> is unconnected or connected to loadless signal.
|
|
Summary:
|
|
no macro.
|
|
Unit <lm32_2nd> synthesized.
|
|
|
|
Synthesizing Unit <Dum_mnic>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
g_dpram_size = 20480
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <dpram_wbb_o_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <dpram_wbb_i_adr<31:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <Dum_mnic> synthesized.
|
|
|
|
Synthesizing Unit <DummySlave>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
Summary:
|
|
no macro.
|
|
Unit <DummySlave> synthesized.
|
|
|
|
Synthesizing Unit <xwb_lm32>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd".
|
|
g_profile = "medium_icache_debug"
|
|
WARNING:Xst:647 - Input <dwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <iwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <I_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <D_CTI_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <D_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <I_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <I_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <D_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\xwb_lm32.vhd" line 491: Output port <D_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
|
|
Found 3-bit register for signal <inst_remaining>.
|
|
Found 32-bit register for signal <inst_addr_reg>.
|
|
Found 1-bit register for signal <data_was_busy>.
|
|
Found 1-bit register for signal <data_remaining>.
|
|
Found 32-bit register for signal <data_addr_reg>.
|
|
Found 1-bit register for signal <inst_was_busy>.
|
|
Found 2-bit subtractor for signal <n0267> created at line 688.
|
|
Found 32-bit adder for signal <inst_addr_reg[31]_GND_23_o_add_9_OUT> created at line 1241.
|
|
Found 32-bit adder for signal <data_addr_reg[31]_GND_23_o_add_20_OUT> created at line 1241.
|
|
Found 3-bit subtractor for signal <GND_23_o_GND_23_o_sub_11_OUT<2:0>> created at line 650.
|
|
Summary:
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 70 D-type flip-flop(s).
|
|
inferred 74 Multiplexer(s).
|
|
Unit <xwb_lm32> synthesized.
|
|
|
|
Synthesizing Unit <lm32_top_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" line 39165: Output port <jrstn> of the instance <jtag_cores> is unconnected or connected to loadless signal.
|
|
Summary:
|
|
no macro.
|
|
Unit <lm32_top_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_cpu_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
eba_reset = 32'b00000000000000000000000000000000
|
|
deba_reset = 32'b00010000000000000000000000000000
|
|
icache_associativity = 1
|
|
icache_sets = 256
|
|
icache_bytes_per_line = 16
|
|
icache_base_address = 32'b00000000000000000000000000000000
|
|
icache_limit = 32'b01111111111111111111111111111111
|
|
dcache_associativity = 1
|
|
dcache_sets = 512
|
|
dcache_bytes_per_line = 16
|
|
dcache_base_address = 0
|
|
dcache_limit = 0
|
|
watchpoints = 32'b00000000000000000000000000000100
|
|
breakpoints = 0
|
|
interrupts = 32
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" line 41048: Output port <pc_w> of the instance <instruction_unit> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v" line 41158: Output port <x_result_sel_logic> of the instance <decoder> is unconnected or connected to loadless signal.
|
|
Found 1-bit register for signal <regfile_raw_1>.
|
|
Found 32-bit register for signal <w_result_d>.
|
|
Found 23-bit register for signal <eba>.
|
|
Found 23-bit register for signal <deba>.
|
|
Found 1-bit register for signal <valid_f>.
|
|
Found 1-bit register for signal <valid_d>.
|
|
Found 1-bit register for signal <valid_x>.
|
|
Found 1-bit register for signal <valid_m>.
|
|
Found 1-bit register for signal <valid_w>.
|
|
Found 32-bit register for signal <operand_0_x>.
|
|
Found 32-bit register for signal <operand_1_x>.
|
|
Found 32-bit register for signal <store_operand_x>.
|
|
Found 29-bit register for signal <branch_target_x>.
|
|
Found 1-bit register for signal <x_result_sel_csr_x>.
|
|
Found 1-bit register for signal <x_result_sel_sext_x>.
|
|
Found 1-bit register for signal <x_result_sel_add_x>.
|
|
Found 1-bit register for signal <m_result_sel_compare_x>.
|
|
Found 1-bit register for signal <m_result_sel_shift_x>.
|
|
Found 1-bit register for signal <w_result_sel_load_x>.
|
|
Found 1-bit register for signal <w_result_sel_mul_x>.
|
|
Found 1-bit register for signal <x_bypass_enable_x>.
|
|
Found 1-bit register for signal <m_bypass_enable_x>.
|
|
Found 1-bit register for signal <write_enable_x>.
|
|
Found 5-bit register for signal <write_idx_x>.
|
|
Found 5-bit register for signal <csr_x>.
|
|
Found 1-bit register for signal <load_x>.
|
|
Found 1-bit register for signal <store_x>.
|
|
Found 2-bit register for signal <size_x>.
|
|
Found 1-bit register for signal <sign_extend_x>.
|
|
Found 1-bit register for signal <adder_op_x>.
|
|
Found 1-bit register for signal <adder_op_x_n>.
|
|
Found 4-bit register for signal <logic_op_x>.
|
|
Found 1-bit register for signal <direction_x>.
|
|
Found 1-bit register for signal <branch_x>.
|
|
Found 1-bit register for signal <branch_predict_x>.
|
|
Found 1-bit register for signal <branch_predict_taken_x>.
|
|
Found 3-bit register for signal <condition_x>.
|
|
Found 1-bit register for signal <break_x>.
|
|
Found 1-bit register for signal <system_call_exception>.
|
|
Found 1-bit register for signal <eret_x>.
|
|
Found 1-bit register for signal <bret_x>.
|
|
Found 1-bit register for signal <csr_write_enable_x>.
|
|
Found 32-bit register for signal <operand_m>.
|
|
Found 29-bit register for signal <branch_target_m>.
|
|
Found 1-bit register for signal <m_result_sel_compare_m>.
|
|
Found 1-bit register for signal <m_result_sel_shift_m>.
|
|
Found 1-bit register for signal <w_result_sel_load_m>.
|
|
Found 1-bit register for signal <w_result_sel_mul_m>.
|
|
Found 1-bit register for signal <m_bypass_enable_m>.
|
|
Found 1-bit register for signal <branch_m>.
|
|
Found 1-bit register for signal <branch_predict_m>.
|
|
Found 1-bit register for signal <branch_predict_taken_m>.
|
|
Found 1-bit register for signal <exception_m>.
|
|
Found 1-bit register for signal <load_m>.
|
|
Found 1-bit register for signal <store_m>.
|
|
Found 1-bit register for signal <write_enable_m>.
|
|
Found 5-bit register for signal <write_idx_m>.
|
|
Found 1-bit register for signal <condition_met_m>.
|
|
Found 1-bit register for signal <debug_exception_m>.
|
|
Found 1-bit register for signal <non_debug_exception_m>.
|
|
Found 32-bit register for signal <operand_w>.
|
|
Found 1-bit register for signal <w_result_sel_load_w>.
|
|
Found 1-bit register for signal <w_result_sel_mul_w>.
|
|
Found 5-bit register for signal <write_idx_w>.
|
|
Found 1-bit register for signal <write_enable_w>.
|
|
Found 1-bit register for signal <debug_exception_w>.
|
|
Found 1-bit register for signal <non_debug_exception_w>.
|
|
Found 1-bit register for signal <use_buf>.
|
|
Found 32-bit register for signal <reg_data_buf_0>.
|
|
Found 32-bit register for signal <reg_data_buf_1>.
|
|
Found 1-bit register for signal <regfile_raw_0>.
|
|
Found 29-bit adder for signal <branch_target_d> created at line 41845.
|
|
Found 32-bit 3-to-1 multiplexer for signal <d_result_1> created at line 41856.
|
|
Found 1-bit 8-to-1 multiplexer for signal <condition_met_x> created at line 41893.
|
|
Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[25]_equal_1_o> created at line 41596
|
|
Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[20]_equal_2_o> created at line 41602
|
|
Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_0_d[4]_equal_11_o> created at line 41783
|
|
Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_0_d[4]_equal_13_o> created at line 41784
|
|
Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_0_d[4]_equal_15_o> created at line 41785
|
|
Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_1_d[4]_equal_17_o> created at line 41786
|
|
Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_1_d[4]_equal_19_o> created at line 41787
|
|
Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_1_d[4]_equal_21_o> created at line 41788
|
|
Found 32-bit comparator equal for signal <cmp_zero> created at line 41887
|
|
Found 1-bit comparator equal for signal <cmp_negative_cmp_overflow_equal_55_o> created at line 41900
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 441 D-type flip-flop(s).
|
|
inferred 10 Comparator(s).
|
|
inferred 74 Multiplexer(s).
|
|
Unit <lm32_cpu_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_instruction_unit_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
associativity = 1
|
|
sets = 256
|
|
bytes_per_line = 16
|
|
base_address = 32'b00000000000000000000000000000000
|
|
limit = 32'b01111111111111111111111111111111
|
|
WARNING:Xst:647 - Input <i_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 29-bit register for signal <pc_d>.
|
|
Found 29-bit register for signal <pc_x>.
|
|
Found 29-bit register for signal <pc_m>.
|
|
Found 29-bit register for signal <pc_w>.
|
|
Found 29-bit register for signal <restart_address>.
|
|
Found 1-bit register for signal <i_cyc_o>.
|
|
Found 1-bit register for signal <i_stb_o>.
|
|
Found 32-bit register for signal <i_adr_o>.
|
|
Found 3-bit register for signal <i_cti_o>.
|
|
Found 1-bit register for signal <i_lock_o>.
|
|
Found 32-bit register for signal <icache_refill_data>.
|
|
Found 1-bit register for signal <icache_refill_ready>.
|
|
Found 1-bit register for signal <i_we_o>.
|
|
Found 4-bit register for signal <i_sel_o>.
|
|
Found 1-bit register for signal <jtag_access>.
|
|
Found 32-bit register for signal <i_dat_o>.
|
|
Found 32-bit register for signal <instruction_d>.
|
|
Found 29-bit register for signal <pc_f>.
|
|
Found 29-bit adder for signal <pc_f[30]_GND_27_o_add_9_OUT> created at line 48975.
|
|
Found 2-bit adder for signal <i_adr_o[3]_GND_27_o_add_58_OUT> created at line 49205.
|
|
Found 8-bit 4-to-1 multiplexer for signal <jtag_read_data> created at line 49137.
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 314 D-type flip-flop(s).
|
|
inferred 17 Multiplexer(s).
|
|
Unit <lm32_instruction_unit_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_icache_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
associativity = 1
|
|
sets = 256
|
|
bytes_per_line = 16
|
|
base_address = 32'b00000000000000000000000000000000
|
|
limit = 32'b01111111111111111111111111111111
|
|
WARNING:Xst:647 - Input <address_a<30:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 4-bit register for signal <state>.
|
|
Found 8-bit register for signal <flush_set>.
|
|
Found 29-bit register for signal <refill_address>.
|
|
Found 1-bit register for signal <restart_request>.
|
|
Found 2-bit register for signal <refill_offset>.
|
|
Found 1-bit register for signal <refilling>.
|
|
Found finite state machine <FSM_0> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 18 |
|
|
| Inputs | 11 |
|
|
| Outputs | 8 |
|
|
| Clock | clk_i (rising_edge) |
|
|
| Reset | rst_i (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 0001 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 8-bit subtractor for signal <flush_set[7]_GND_28_o_sub_22_OUT> created at line 46396.
|
|
Found 2-bit adder for signal <refill_offset[3]_GND_28_o_add_59_OUT> created at line 46473.
|
|
Found 20-bit comparator equal for signal <way_match> created at line 46278
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 41 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
inferred 8 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <lm32_icache_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_ram_1>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_ram.v".
|
|
data_width = 32
|
|
address_width = 10
|
|
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1024x32-bit dual-port RAM <Mram_mem> for signal <mem>.
|
|
Found 10-bit register for signal <ra>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 10 D-type flip-flop(s).
|
|
Unit <lm32_ram_1> synthesized.
|
|
|
|
Synthesizing Unit <lm32_ram_2>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_ram.v".
|
|
data_width = 20
|
|
address_width = 8
|
|
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 256x20-bit dual-port RAM <Mram_mem> for signal <mem>.
|
|
Found 8-bit register for signal <ra>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 8 D-type flip-flop(s).
|
|
Unit <lm32_ram_2> synthesized.
|
|
|
|
Synthesizing Unit <lm32_decoder_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
Summary:
|
|
inferred 10 Multiplexer(s).
|
|
Unit <lm32_decoder_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_load_store_unit_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
associativity = 1
|
|
sets = 512
|
|
bytes_per_line = 16
|
|
base_address = 0
|
|
limit = 0
|
|
WARNING:Xst:647 - Input <load_store_address_x<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <stall_a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <kill_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <load_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <store_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <store_q_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <d_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1-bit register for signal <d_stb_o>.
|
|
Found 32-bit register for signal <d_dat_o>.
|
|
Found 32-bit register for signal <d_adr_o>.
|
|
Found 4-bit register for signal <d_sel_o>.
|
|
Found 1-bit register for signal <d_we_o>.
|
|
Found 1-bit register for signal <d_lock_o>.
|
|
Found 32-bit register for signal <wb_data_m>.
|
|
Found 1-bit register for signal <wb_load_complete>.
|
|
Found 1-bit register for signal <stall_wb_load>.
|
|
Found 1-bit register for signal <sign_extend_m>.
|
|
Found 2-bit register for signal <size_m>.
|
|
Found 4-bit register for signal <byte_enable_m>.
|
|
Found 32-bit register for signal <store_data_m>.
|
|
Found 1-bit register for signal <wb_select_m>.
|
|
Found 2-bit register for signal <size_w>.
|
|
Found 32-bit register for signal <data_w>.
|
|
Found 1-bit register for signal <sign_extend_w>.
|
|
Found 1-bit register for signal <d_cyc_o>.
|
|
Found 32-bit 3-to-1 multiplexer for signal <store_data_x> created at line 44146.
|
|
Summary:
|
|
inferred 180 D-type flip-flop(s).
|
|
inferred 2 Multiplexer(s).
|
|
Unit <lm32_load_store_unit_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_adder>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_adder.v".
|
|
Summary:
|
|
no macro.
|
|
Unit <lm32_adder> synthesized.
|
|
|
|
Synthesizing Unit <lm32_addsub>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_addsub.v".
|
|
Found 33-bit subtractor for signal <GND_34_o_GND_34_o_sub_3_OUT> created at line 69.
|
|
Found 33-bit subtractor for signal <tmp_subResult> created at line 69.
|
|
Found 33-bit adder for signal <n0025> created at line 68.
|
|
Found 33-bit adder for signal <tmp_addResult> created at line 68.
|
|
Summary:
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 2 Multiplexer(s).
|
|
Unit <lm32_addsub> synthesized.
|
|
|
|
Synthesizing Unit <lm32_logic_op>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_logic_op.v".
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<0>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<1>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<2>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<3>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<4>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<5>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<6>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<7>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<8>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<9>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<10>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<11>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<12>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<13>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<14>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<15>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<16>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<17>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<18>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<19>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<20>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<21>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<22>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<23>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<24>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<25>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<26>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<27>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<28>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<29>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<30>> created at line 72.
|
|
Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<31>> created at line 72.
|
|
Summary:
|
|
inferred 32 Multiplexer(s).
|
|
Unit <lm32_logic_op> synthesized.
|
|
|
|
Synthesizing Unit <lm32_shifter>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_shifter.v".
|
|
WARNING:Xst:647 - Input <operand_1_x<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1-bit register for signal <direction_m>.
|
|
Found 32-bit register for signal <right_shift_result>.
|
|
Found 64-bit shifter logical right for signal <n0028> created at line 128
|
|
Summary:
|
|
inferred 33 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
inferred 1 Combinational logic shifter(s).
|
|
Unit <lm32_shifter> synthesized.
|
|
|
|
Synthesizing Unit <lm32_multiplier>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\platform\kintex7\lm32_multiplier.v".
|
|
Found 16-bit register for signal <a1>.
|
|
Found 16-bit register for signal <b0>.
|
|
Found 16-bit register for signal <b1>.
|
|
Found 16-bit register for signal <c0>.
|
|
Found 16-bit register for signal <c1>.
|
|
Found 16-bit register for signal <d1>.
|
|
Found 16-bit register for signal <e1>.
|
|
Found 16-bit register for signal <result0>.
|
|
Found 16-bit register for signal <result1>.
|
|
Found 16-bit register for signal <a0>.
|
|
Found 16-bit adder for signal <n0077> created at line 116.
|
|
Found 16-bit adder for signal <c1[15]_e1[15]_add_17_OUT> created at line 116.
|
|
Found 16x16-bit multiplier for signal <a0[15]_b0[15]_MuLt_9_OUT> created at line 110.
|
|
Found 16x16-bit multiplier for signal <n0055> created at line 111.
|
|
Found 16x16-bit multiplier for signal <n0056> created at line 112.
|
|
Summary:
|
|
inferred 3 Multiplier(s).
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 160 D-type flip-flop(s).
|
|
Unit <lm32_multiplier> synthesized.
|
|
|
|
Synthesizing Unit <lm32_interrupt_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
interrupts = 32
|
|
Found 1-bit register for signal <eie>.
|
|
Found 1-bit register for signal <bie>.
|
|
Found 32-bit register for signal <im>.
|
|
Found 32-bit register for signal <ip>.
|
|
Found 11-bit register for signal <eie_delay>.
|
|
Found 1-bit register for signal <ie>.
|
|
Found 32-bit 3-to-1 multiplexer for signal <csr_read_data> created at line 50677.
|
|
Summary:
|
|
inferred 78 D-type flip-flop(s).
|
|
inferred 17 Multiplexer(s).
|
|
Unit <lm32_interrupt_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_jtag_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
WARNING:Xst:647 - Input <csr_write_data<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <jtag_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1-bit register for signal <rx_update_r>.
|
|
Found 1-bit register for signal <rx_update_r_r>.
|
|
Found 1-bit register for signal <rx_update_r_r_r>.
|
|
Found 4-bit register for signal <state>.
|
|
Found 4-bit register for signal <command>.
|
|
Found 8-bit register for signal <jtag_reg_d>.
|
|
Found 1-bit register for signal <processing>.
|
|
Found 1-bit register for signal <jtag_csr_write_enable>.
|
|
Found 1-bit register for signal <jtag_read_enable>.
|
|
Found 1-bit register for signal <jtag_write_enable>.
|
|
Found 1-bit register for signal <jtag_break>.
|
|
Found 1-bit register for signal <jtag_reset>.
|
|
Found 8-bit register for signal <uart_tx_byte>.
|
|
Found 1-bit register for signal <uart_tx_valid>.
|
|
Found 8-bit register for signal <uart_rx_byte>.
|
|
Found 1-bit register for signal <uart_rx_valid>.
|
|
Found 8-bit register for signal <jtag_byte_4>.
|
|
Found 8-bit register for signal <jtag_byte_3>.
|
|
Found 8-bit register for signal <jtag_byte_2>.
|
|
Found 8-bit register for signal <jtag_byte_1>.
|
|
Found 8-bit register for signal <jtag_byte_0>.
|
|
Found 1-bit register for signal <rx_update>.
|
|
Found finite state machine <FSM_1> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 9 |
|
|
| Transitions | 36 |
|
|
| Inputs | 13 |
|
|
| Outputs | 8 |
|
|
| Clock | clk_i (rising_edge) |
|
|
| Reset | rst_i (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 0000 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit adder for signal <jtag_byte_2[7]_GND_40_o_add_22_OUT> created at line 50096.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 80 D-type flip-flop(s).
|
|
inferred 13 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <lm32_jtag_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_debug_medium_icache_debug>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\generated\lm32_allprofiles.v".
|
|
breakpoints = 0
|
|
watchpoints = 32'b00000000000000000000000000000100
|
|
WARNING:Xst:647 - Input <pc_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1-bit register for signal <wp<0><30>>.
|
|
Found 1-bit register for signal <wp<0><29>>.
|
|
Found 1-bit register for signal <wp<0><28>>.
|
|
Found 1-bit register for signal <wp<0><27>>.
|
|
Found 1-bit register for signal <wp<0><26>>.
|
|
Found 1-bit register for signal <wp<0><25>>.
|
|
Found 1-bit register for signal <wp<0><24>>.
|
|
Found 1-bit register for signal <wp<0><23>>.
|
|
Found 1-bit register for signal <wp<0><22>>.
|
|
Found 1-bit register for signal <wp<0><21>>.
|
|
Found 1-bit register for signal <wp<0><20>>.
|
|
Found 1-bit register for signal <wp<0><19>>.
|
|
Found 1-bit register for signal <wp<0><18>>.
|
|
Found 1-bit register for signal <wp<0><17>>.
|
|
Found 1-bit register for signal <wp<0><16>>.
|
|
Found 1-bit register for signal <wp<0><15>>.
|
|
Found 1-bit register for signal <wp<0><14>>.
|
|
Found 1-bit register for signal <wp<0><13>>.
|
|
Found 1-bit register for signal <wp<0><12>>.
|
|
Found 1-bit register for signal <wp<0><11>>.
|
|
Found 1-bit register for signal <wp<0><10>>.
|
|
Found 1-bit register for signal <wp<0><9>>.
|
|
Found 1-bit register for signal <wp<0><8>>.
|
|
Found 1-bit register for signal <wp<0><7>>.
|
|
Found 1-bit register for signal <wp<0><6>>.
|
|
Found 1-bit register for signal <wp<0><5>>.
|
|
Found 1-bit register for signal <wp<0><4>>.
|
|
Found 1-bit register for signal <wp<0><3>>.
|
|
Found 1-bit register for signal <wp<0><2>>.
|
|
Found 1-bit register for signal <wp<0><1>>.
|
|
Found 1-bit register for signal <wp<0><0>>.
|
|
Found 1-bit register for signal <wpc_c<0><1>>.
|
|
Found 1-bit register for signal <wpc_c<0><0>>.
|
|
Found 1-bit register for signal <wp<1><31>>.
|
|
Found 1-bit register for signal <wp<1><30>>.
|
|
Found 1-bit register for signal <wp<1><29>>.
|
|
Found 1-bit register for signal <wp<1><28>>.
|
|
Found 1-bit register for signal <wp<1><27>>.
|
|
Found 1-bit register for signal <wp<1><26>>.
|
|
Found 1-bit register for signal <wp<1><25>>.
|
|
Found 1-bit register for signal <wp<1><24>>.
|
|
Found 1-bit register for signal <wp<1><23>>.
|
|
Found 1-bit register for signal <wp<1><22>>.
|
|
Found 1-bit register for signal <wp<1><21>>.
|
|
Found 1-bit register for signal <wp<1><20>>.
|
|
Found 1-bit register for signal <wp<1><19>>.
|
|
Found 1-bit register for signal <wp<1><18>>.
|
|
Found 1-bit register for signal <wp<1><17>>.
|
|
Found 1-bit register for signal <wp<1><16>>.
|
|
Found 1-bit register for signal <wp<1><15>>.
|
|
Found 1-bit register for signal <wp<1><14>>.
|
|
Found 1-bit register for signal <wp<1><13>>.
|
|
Found 1-bit register for signal <wp<1><12>>.
|
|
Found 1-bit register for signal <wp<1><11>>.
|
|
Found 1-bit register for signal <wp<1><10>>.
|
|
Found 1-bit register for signal <wp<1><9>>.
|
|
Found 1-bit register for signal <wp<1><8>>.
|
|
Found 1-bit register for signal <wp<1><7>>.
|
|
Found 1-bit register for signal <wp<1><6>>.
|
|
Found 1-bit register for signal <wp<1><5>>.
|
|
Found 1-bit register for signal <wp<1><4>>.
|
|
Found 1-bit register for signal <wp<1><3>>.
|
|
Found 1-bit register for signal <wp<1><2>>.
|
|
Found 1-bit register for signal <wp<1><1>>.
|
|
Found 1-bit register for signal <wp<1><0>>.
|
|
Found 1-bit register for signal <wpc_c<1><1>>.
|
|
Found 1-bit register for signal <wpc_c<1><0>>.
|
|
Found 1-bit register for signal <wp<2><31>>.
|
|
Found 1-bit register for signal <wp<2><30>>.
|
|
Found 1-bit register for signal <wp<2><29>>.
|
|
Found 1-bit register for signal <wp<2><28>>.
|
|
Found 1-bit register for signal <wp<2><27>>.
|
|
Found 1-bit register for signal <wp<2><26>>.
|
|
Found 1-bit register for signal <wp<2><25>>.
|
|
Found 1-bit register for signal <wp<2><24>>.
|
|
Found 1-bit register for signal <wp<2><23>>.
|
|
Found 1-bit register for signal <wp<2><22>>.
|
|
Found 1-bit register for signal <wp<2><21>>.
|
|
Found 1-bit register for signal <wp<2><20>>.
|
|
Found 1-bit register for signal <wp<2><19>>.
|
|
Found 1-bit register for signal <wp<2><18>>.
|
|
Found 1-bit register for signal <wp<2><17>>.
|
|
Found 1-bit register for signal <wp<2><16>>.
|
|
Found 1-bit register for signal <wp<2><15>>.
|
|
Found 1-bit register for signal <wp<2><14>>.
|
|
Found 1-bit register for signal <wp<2><13>>.
|
|
Found 1-bit register for signal <wp<2><12>>.
|
|
Found 1-bit register for signal <wp<2><11>>.
|
|
Found 1-bit register for signal <wp<2><10>>.
|
|
Found 1-bit register for signal <wp<2><9>>.
|
|
Found 1-bit register for signal <wp<2><8>>.
|
|
Found 1-bit register for signal <wp<2><7>>.
|
|
Found 1-bit register for signal <wp<2><6>>.
|
|
Found 1-bit register for signal <wp<2><5>>.
|
|
Found 1-bit register for signal <wp<2><4>>.
|
|
Found 1-bit register for signal <wp<2><3>>.
|
|
Found 1-bit register for signal <wp<2><2>>.
|
|
Found 1-bit register for signal <wp<2><1>>.
|
|
Found 1-bit register for signal <wp<2><0>>.
|
|
Found 1-bit register for signal <wpc_c<2><1>>.
|
|
Found 1-bit register for signal <wpc_c<2><0>>.
|
|
Found 1-bit register for signal <wp<3><31>>.
|
|
Found 1-bit register for signal <wp<3><30>>.
|
|
Found 1-bit register for signal <wp<3><29>>.
|
|
Found 1-bit register for signal <wp<3><28>>.
|
|
Found 1-bit register for signal <wp<3><27>>.
|
|
Found 1-bit register for signal <wp<3><26>>.
|
|
Found 1-bit register for signal <wp<3><25>>.
|
|
Found 1-bit register for signal <wp<3><24>>.
|
|
Found 1-bit register for signal <wp<3><23>>.
|
|
Found 1-bit register for signal <wp<3><22>>.
|
|
Found 1-bit register for signal <wp<3><21>>.
|
|
Found 1-bit register for signal <wp<3><20>>.
|
|
Found 1-bit register for signal <wp<3><19>>.
|
|
Found 1-bit register for signal <wp<3><18>>.
|
|
Found 1-bit register for signal <wp<3><17>>.
|
|
Found 1-bit register for signal <wp<3><16>>.
|
|
Found 1-bit register for signal <wp<3><15>>.
|
|
Found 1-bit register for signal <wp<3><14>>.
|
|
Found 1-bit register for signal <wp<3><13>>.
|
|
Found 1-bit register for signal <wp<3><12>>.
|
|
Found 1-bit register for signal <wp<3><11>>.
|
|
Found 1-bit register for signal <wp<3><10>>.
|
|
Found 1-bit register for signal <wp<3><9>>.
|
|
Found 1-bit register for signal <wp<3><8>>.
|
|
Found 1-bit register for signal <wp<3><7>>.
|
|
Found 1-bit register for signal <wp<3><6>>.
|
|
Found 1-bit register for signal <wp<3><5>>.
|
|
Found 1-bit register for signal <wp<3><4>>.
|
|
Found 1-bit register for signal <wp<3><3>>.
|
|
Found 1-bit register for signal <wp<3><2>>.
|
|
Found 1-bit register for signal <wp<3><1>>.
|
|
Found 1-bit register for signal <wp<3><0>>.
|
|
Found 1-bit register for signal <wpc_c<3><1>>.
|
|
Found 1-bit register for signal <wpc_c<3><0>>.
|
|
Found 1-bit register for signal <dc_re>.
|
|
Found 3-bit register for signal <state>.
|
|
Found 1-bit register for signal <dc_ss>.
|
|
Found 1-bit register for signal <wp<0><31>>.
|
|
Found finite state machine <FSM_2> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 36 |
|
|
| Inputs | 8 |
|
|
| Outputs | 4 |
|
|
| Clock | clk_i (rising_edge) |
|
|
| Reset | rst_i (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 000 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 32-bit comparator equal for signal <wp[0][31]_load_store_address_x[31]_equal_2_o> created at line 47904
|
|
Found 32-bit comparator equal for signal <wp[1][31]_load_store_address_x[31]_equal_3_o> created at line 47904
|
|
Found 32-bit comparator equal for signal <wp[2][31]_load_store_address_x[31]_equal_4_o> created at line 47904
|
|
Found 32-bit comparator equal for signal <wp[3][31]_load_store_address_x[31]_equal_5_o> created at line 47904
|
|
Summary:
|
|
inferred 138 D-type flip-flop(s).
|
|
inferred 4 Comparator(s).
|
|
inferred 35 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <lm32_debug_medium_icache_debug> synthesized.
|
|
|
|
Synthesizing Unit <lm32_dp_ram>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\lm32_dp_ram.v".
|
|
addr_width = 5
|
|
addr_depth = 32
|
|
data_width = 32
|
|
WARNING:Xst:647 - Input <rst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 32x32-bit dual-port RAM <Mram_ram> for signal <ram>.
|
|
Found 5-bit register for signal <raddr_r>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 5 D-type flip-flop(s).
|
|
Unit <lm32_dp_ram> synthesized.
|
|
|
|
Synthesizing Unit <jtag_cores>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\src\jtag_cores.v".
|
|
Found 11-bit register for signal <jtag_latched>.
|
|
Found 11-bit register for signal <jtag_shift>.
|
|
Summary:
|
|
inferred 22 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
Unit <jtag_cores> synthesized.
|
|
|
|
Synthesizing Unit <jtag_tap>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_lm32\platform\kintex7\jtag_tap.v".
|
|
Found 1-bit register for signal <update_delay>.
|
|
Summary:
|
|
inferred 1 D-type flip-flop(s).
|
|
Unit <jtag_tap> synthesized.
|
|
|
|
Synthesizing Unit <xwb_dpram>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd".
|
|
g_size = 20480
|
|
g_init_file = "lm32_memory.ldr"
|
|
g_init_value = ""
|
|
g_must_have_init_file = true
|
|
g_slave1_interface_mode = pipelined
|
|
g_slave2_interface_mode = pipelined
|
|
g_slave1_granularity = byte
|
|
g_slave2_granularity = word
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_adr_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_sel_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_err_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_rty_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_ack_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_stall_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <sl_int_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_cyc_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_stb_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 80: Output port <ma_we_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_adr_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_sel_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_err_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_rty_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_ack_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_stall_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <sl_int_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_cyc_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_stb_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_dpram\xwb_dpram.vhd" line 96: Output port <ma_we_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <slave1_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <slave2_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <slave2_out_ack>.
|
|
Found 1-bit register for signal <slave1_out_ack>.
|
|
Summary:
|
|
inferred 2 D-type flip-flop(s).
|
|
inferred 2 Multiplexer(s).
|
|
Unit <xwb_dpram> synthesized.
|
|
|
|
Synthesizing Unit <wb_slave_adapter_1>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd".
|
|
g_master_use_struct = true
|
|
g_master_mode = pipelined
|
|
g_master_granularity = word
|
|
g_slave_use_struct = true
|
|
g_slave_mode = pipelined
|
|
g_slave_granularity = byte
|
|
WARNING:Xst:647 - Input <sl_adr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_sel_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_slave_adapter_1> synthesized.
|
|
|
|
Synthesizing Unit <wb_slave_adapter_2>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd".
|
|
g_master_use_struct = true
|
|
g_master_mode = pipelined
|
|
g_master_granularity = word
|
|
g_slave_use_struct = true
|
|
g_slave_mode = pipelined
|
|
g_slave_granularity = word
|
|
WARNING:Xst:647 - Input <sl_adr_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_sel_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_slave_adapter_2> synthesized.
|
|
|
|
Synthesizing Unit <generic_dpram>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram.vhd".
|
|
g_data_width = 32
|
|
g_size = 20480
|
|
g_with_byte_enable = true
|
|
g_addr_conflict_resolution = "read_first"
|
|
g_init_file = "lm32_memory.ldr"
|
|
g_init_value = ""
|
|
g_dual_clock = false
|
|
g_fail_if_file_not_found = true
|
|
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Summary:
|
|
no macro.
|
|
Unit <generic_dpram> synthesized.
|
|
|
|
Synthesizing Unit <generic_dpram_sameclock>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\genrams\xilinx\generic_dpram_sameclock.vhd".
|
|
g_data_width = 32
|
|
g_size = 20480
|
|
g_with_byte_enable = true
|
|
g_addr_conflict_resolution = "read_first"
|
|
g_init_file = "lm32_memory.ldr"
|
|
g_init_value = ""
|
|
g_fail_if_file_not_found = true
|
|
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:3035 - Index value(s) does not match array range for signal <ram>, simulation mismatch.
|
|
Found 20480x32-bit dual-port RAM <Mram_ram> for signal <ram>.
|
|
Found 32-bit register for signal <qb_o>.
|
|
Found 32-bit register for signal <qa_o>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 64 D-type flip-flop(s).
|
|
inferred 8 Multiplexer(s).
|
|
Unit <generic_dpram_sameclock> synthesized.
|
|
|
|
Synthesizing Unit <xwb_sdb_crossbar_1>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_sdb_crossbar.vhd".
|
|
g_num_masters = 3
|
|
g_num_slaves = 2
|
|
g_registered = true
|
|
g_wraparound = true
|
|
g_layout =
|
|
("00000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000111111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000000100000000
|
|
00001")
|
|
g_sdb_addr = "00000000000000110000000000000000"
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_sdb_crossbar_1> synthesized.
|
|
|
|
Synthesizing Unit <sdb_rom_1>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\sdb_rom.vhd".
|
|
g_layout =
|
|
("00000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000111111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000000100000000
|
|
00001")
|
|
g_bus_end = "0000000000000000000000000000000000000000000000111111111111111111"
|
|
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value.
|
|
Found 64x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
|
|
Found 1-bit register for signal <slave_o_ack>.
|
|
Found 6-bit register for signal <adr_reg>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 7 D-type flip-flop(s).
|
|
Unit <sdb_rom_1> synthesized.
|
|
|
|
Synthesizing Unit <xwb_crossbar_1>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_crossbar.vhd".
|
|
g_num_masters = 3
|
|
g_num_slaves = 3
|
|
g_registered = true
|
|
g_address = ("00000000000000110000000000000000","00000000000000100000000000000000","00000000000000000000000000000000")
|
|
g_mask = ("00000000000000111111111100000000","00000000000000111110000000000000","00000000000000100000000000000000")
|
|
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 4-bit register for signal <matrix_old<2>>.
|
|
Found 4-bit register for signal <matrix_old<1>>.
|
|
Found 4-bit register for signal <matrix_old<0>>.
|
|
Found 1-bit register for signal <virtual_ERR>.
|
|
Summary:
|
|
inferred 13 D-type flip-flop(s).
|
|
inferred 12 Multiplexer(s).
|
|
Unit <xwb_crossbar_1> synthesized.
|
|
|
|
Synthesizing Unit <xwb_sdb_crossbar_2>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_sdb_crossbar.vhd".
|
|
g_num_masters = 1
|
|
g_num_slaves = 16
|
|
g_registered = true
|
|
g_wraparound = true
|
|
g_layout =
|
|
("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000111100000000000000000000000000000000000000000000000000000000000011111111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000111011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000000100000000
|
|
00001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000110100000000000000000000000000000000000000000000000000000000000011011111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000000100
|
|
00000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010111111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000
|
|
00010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010011111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111111000000000000000000000000000000000000000000000000111111110000001100100101111001000001101010010011000000000000000000000000000000010010000000010011000001110000000101010000011001010111001001101001011100000110100000100000010001000110000101110100011001010101001001100101011101100010110101001001010001000
|
|
01000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001111111111100000000000000000000000000000000000000000000000011001110010000101110011101001111011111001010000000000000000000000000000000000001001000000001001100000111000000010101011101010010001011010101010001101001011011010110010101110010001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000011011111111000000000000000000000000000000000000000000000000110011100100001001101011100101000101011011100100000000000000000000000000000000010010000000010011000001110000000101010111010100100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001
|
|
00000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001011111111100000000000000000000000000000000000000000000000011001110010000100110101110010100010101101110010000000000000000000000000000000001001000000001001100000111000000010101011101010010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010011111111000000000000000000000000000000000000000000000000110011100100001011011110000001001100101001001101000000000000000000000000000000010010000000010011000001110000000101010111010100100010110101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000100
|
|
00000100000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000111111111100000000000000000000000000000000000000000000000011001110010000101100110111100101001001110110110100000000000000000000000000000001001000000001001100000111000000010101011101010010001011010100011101010000010010010100111100100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000111111110000001011001001101110010000111011100000000000000000000000000000000000010010000000010010000000110000010101010000011001010111001001101001011100000110100000101101010000010100010101010011001000000010000000100000001000000010000
|
|
00010000000100000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000011111111000000010101011010100000001111001001101000000000000000000000000000000001001000000001001100000111000000010101000001100101011100100110100101110000011010000010110101010100010001000100001100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001011100010110100010011110100000100000000000000000000000000000000010010000000010010000000110000010101010111010100100010110101010000011001010111001001101001011100000110100000101101010101010100000101010010010101000
|
|
01000000010000000100000001000000010000000000001")
|
|
g_sdb_addr = "00000000000000000001000000000000"
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_sdb_crossbar_2> synthesized.
|
|
|
|
Synthesizing Unit <sdb_rom_2>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\sdb_rom.vhd".
|
|
g_layout =
|
|
("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000111100000000000000000000000000000000000000000000000000000000000011111111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000111011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000000100000000
|
|
00001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000110100000000000000000000000000000000000000000000000000000000000011011111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000000100
|
|
00000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010111111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101011111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000101000000000000000000000000000000010010000000010010000001100001010101010111010100100010110101010000011001010111001001101001011100000110100000101101010000010111010101111000010101110100001000100000001000000010000
|
|
00010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010011111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100010100000000000000000000000000000001001000000001001000000110000101010101011101010010001011010101000001100101011100100110100101110000011010000010110101000001011101010111100001010111010000100010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100011111111000000000000000000000000000000000000000000000000111111110000001100100101111001000001101010010011000000000000000000000000000000010010000000010011000001110000000101010000011001010111001001101001011100000110100000100000010001000110000101110100011001010101001001100101011101100010110101001001010001000
|
|
01000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001111111111100000000000000000000000000000000000000000000000011001110010000101110011101001111011111001010000000000000000000000000000000000001001000000001001100000111000000010101011101010010001011010101010001101001011011010110010101110010001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000011011111111000000000000000000000000000000000000000000000000110011100100001001101011100101000101011011100100000000000000000000000000000000010010000000010011000001110000000101010111010100100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001
|
|
00000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001011111111100000000000000000000000000000000000000000000000011001110010000100110101110010100010101101110010000000000000000000000000000000001001000000001001100000111000000010101011101010010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010011111111000000000000000000000000000000000000000000000000110011100100001011011110000001001100101001001101000000000000000000000000000000010010000000010011000001110000000101010111010100100010110101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000100
|
|
00000100000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000111111111100000000000000000000000000000000000000000000000011001110010000101100110111100101001001110110110100000000000000000000000000000001001000000001001100000111000000010101011101010010001011010100011101010000010010010100111100100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000111111110000001011001001101110010000111011100000000000000000000000000000000000010010000000010010000000110000010101010000011001010111001001101001011100000110100000101101010000010100010101010011001000000010000000100000001000000010000
|
|
00010000000100000001000000010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000011111111000000010101011010100000001111001001101000000000000000000000000000000001001000000001001100000111000000010101000001100101011100100110100101110000011010000010110101010100010001000100001100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001011100010110100010011110100000100000000000000000000000000000000010010000000010010000000110000010101010111010100100010110101010000011001010111001001101001011100000110100000101101010101010100000101010010010101000
|
|
01000000010000000100000001000000010000000000001")
|
|
g_bus_end = "0000000000000000000000000000000000000000000000000001111111111111"
|
|
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value.
|
|
Found 512x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
|
|
Found 1-bit register for signal <slave_o_ack>.
|
|
Found 9-bit register for signal <adr_reg>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 10 D-type flip-flop(s).
|
|
Unit <sdb_rom_2> synthesized.
|
|
|
|
Synthesizing Unit <xwb_crossbar_2>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_crossbar\xwb_crossbar.vhd".
|
|
g_num_masters = 1
|
|
g_num_slaves = 17
|
|
g_registered = true
|
|
g_address = ("00000000000000000001000000000000","00000000000000000000111100000000","00000000000000000000111000000000","00000000000000000000110100000000","00000000000000000000110000000000","00000000000000000000101100000000","00000000000000000000101000000000","00000000000000000000100100000000","00000000000000000000100000000000","00000000000000000000011100000000","00000000000000000000011000000000","00000000000000000000010100000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000")
|
|
g_mask = ("00000000000000000001100000000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000")
|
|
WARNING:Xst:647 - Input <master_i[16]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[15]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[14]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[13]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[12]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[11]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[10]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[9]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[8]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[7]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[6]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[5]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[4]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[3]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 18-bit register for signal <matrix_old<0>>.
|
|
Found 1-bit register for signal <virtual_ERR>.
|
|
Summary:
|
|
inferred 19 D-type flip-flop(s).
|
|
inferred 18 Multiplexer(s).
|
|
Unit <xwb_crossbar_2> synthesized.
|
|
|
|
Synthesizing Unit <xwb_simple_uart>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\xwb_simple_uart.vhd".
|
|
g_with_virtual_uart = false
|
|
g_with_physical_uart = true
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_simple_uart> synthesized.
|
|
|
|
Synthesizing Unit <wb_simple_uart>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd".
|
|
g_with_virtual_uart = false
|
|
g_with_physical_uart = true
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 152: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 175: Output port <regs_o_host_tdr_data_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 175: Output port <host_rack_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\wb_simple_uart.vhd" line 226: Output port <rx_error_o> of the instance <gen_phys_uart.U_RX> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <regs_in_host_rdr_data_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <regs_in_host_rdr_count_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <regs_in_host_tdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <regs_in_host_rdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <regs_in_sr_rx_rdy_i>.
|
|
Found 8-bit register for signal <regs_in_rdr_rx_data_i>.
|
|
Found 32-bit register for signal <uart_bcr>.
|
|
Summary:
|
|
inferred 41 D-type flip-flop(s).
|
|
Unit <wb_simple_uart> synthesized.
|
|
|
|
Synthesizing Unit <wb_slave_adapter_3>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd".
|
|
g_master_use_struct = true
|
|
g_master_mode = classic
|
|
g_master_granularity = word
|
|
g_slave_use_struct = false
|
|
g_slave_mode = pipelined
|
|
g_slave_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <stored_we>.
|
|
Found 1-bit register for signal <fsm_state>.
|
|
Summary:
|
|
inferred 2 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
Unit <wb_slave_adapter_3> synthesized.
|
|
|
|
Synthesizing Unit <simple_uart_wb>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\simple_uart_wb.vhd".
|
|
WARNING:Xst:647 - Input <wb_sel_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 8-bit register for signal <ack_sreg>.
|
|
Found 32-bit register for signal <rddata_reg>.
|
|
Found 1-bit register for signal <ack_in_progress>.
|
|
Found 1-bit register for signal <regs_o_bcr_wr_o>.
|
|
Found 1-bit register for signal <regs_o_tdr_tx_data_wr_o>.
|
|
Found 1-bit register for signal <regs_o_host_tdr_data_wr_o>.
|
|
Found 1-bit register for signal <rdr_rack_o>.
|
|
Found 1-bit register for signal <host_rack_o>.
|
|
WARNING:Xst:2404 - FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
|
|
WARNING:Xst:2404 - FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
|
|
Summary:
|
|
inferred 46 D-type flip-flop(s).
|
|
inferred 8 Multiplexer(s).
|
|
Unit <simple_uart_wb> synthesized.
|
|
|
|
Synthesizing Unit <uart_baud_gen>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_baud_gen.vhd".
|
|
g_baud_acc_width = 16
|
|
Found 8-bit register for signal <Baud_sreg>.
|
|
Found 17-bit register for signal <Baud8GeneratorAcc>.
|
|
Found 17-bit adder for signal <GND_86_o_Baud8GeneratorInc[16]_add_1_OUT> created at line 39.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 25 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
Unit <uart_baud_gen> synthesized.
|
|
|
|
Synthesizing Unit <uart_async_tx>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_async_tx.vhd".
|
|
Found 4-bit register for signal <state>.
|
|
Found 1-bit register for signal <TxD>.
|
|
Found 8-bit register for signal <TxD_dataReg>.
|
|
Found finite state machine <FSM_3> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 13 |
|
|
| Transitions | 26 |
|
|
| Inputs | 2 |
|
|
| Outputs | 6 |
|
|
| Clock | clk_sys_i (rising_edge) |
|
|
| Reset | rst_n_i_INV_278_o (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 0000 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit 8-to-1 multiplexer for signal <muxbit> created at line 130.
|
|
Summary:
|
|
inferred 9 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <uart_async_tx> synthesized.
|
|
|
|
Synthesizing Unit <uart_async_rx>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_uart\uart_async_rx.vhd".
|
|
Found 1-bit register for signal <RxD_bit_inv>.
|
|
Found 2-bit register for signal <RxD_cnt_inv>.
|
|
Found 4-bit register for signal <bit_spacing>.
|
|
Found 4-bit register for signal <state>.
|
|
Found 8-bit register for signal <RxD_data>.
|
|
Found 1-bit register for signal <RxD_data_error>.
|
|
Found 1-bit register for signal <RxD_data_ready>.
|
|
Found 2-bit register for signal <RxD_sync_inv>.
|
|
Found finite state machine <FSM_4> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 10 |
|
|
| Transitions | 30 |
|
|
| Inputs | 3 |
|
|
| Outputs | 3 |
|
|
| Clock | clk_sys_i (rising_edge) |
|
|
| Reset | rst_n_i_INV_288_o (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 0000 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 2-bit adder for signal <RxD_cnt_inv[1]_GND_88_o_add_4_OUT> created at line 1241.
|
|
Found 4-bit adder for signal <GND_88_o_GND_88_o_add_16_OUT> created at line 1241.
|
|
Found 2-bit subtractor for signal <GND_88_o_GND_88_o_sub_7_OUT<1:0>> created at line 1308.
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 19 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <uart_async_rx> synthesized.
|
|
|
|
Synthesizing Unit <xwb_tics>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\xwb_tics.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
g_period = 62500
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_tics> synthesized.
|
|
|
|
Synthesizing Unit <wb_tics>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
g_period = 62500
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <master_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_simple_timer\wb_tics.vhd" line 73: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <cntr_overflow>.
|
|
Found 32-bit register for signal <cntr_tics>.
|
|
Found 1-bit register for signal <wb_out_ack>.
|
|
Found 32-bit register for signal <wb_out_dat>.
|
|
Found 24-bit register for signal <cntr_div>.
|
|
Found 24-bit adder for signal <cntr_div[23]_GND_90_o_add_3_OUT> created at line 1241.
|
|
Found 32-bit adder for signal <cntr_tics[31]_GND_90_o_add_7_OUT> created at line 1241.
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 90 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
Unit <wb_tics> synthesized.
|
|
|
|
Synthesizing Unit <xwb_gpio_port>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\xwb_gpio_port.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
g_num_pins = 7
|
|
g_with_builtin_tristates = false
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_gpio_port> synthesized.
|
|
|
|
Synthesizing Unit <wb_gpio_port>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
g_num_pins = 7
|
|
g_with_builtin_tristates = false
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 97: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_gpio_port\wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:2563 - Inout <gpio_b> is never assigned. Tied to value Z.
|
|
WARNING:Xst:653 - Signal <gpio_in_synced<31:7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 32-bit register for signal <out_reg>.
|
|
Found 32-bit register for signal <wb_out_dat>.
|
|
Found 1-bit register for signal <ack_int>.
|
|
Found 32-bit register for signal <dir_reg>.
|
|
Found 8x1-bit Read Only RAM for signal <write_mask<0>>
|
|
Found 7-bit tristate buffer for signal <gpio_b> created at line 56
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 97 D-type flip-flop(s).
|
|
inferred 8 Multiplexer(s).
|
|
inferred 1 Tristate(s).
|
|
Unit <wb_gpio_port> synthesized.
|
|
|
|
Synthesizing Unit <gc_sync_ffs>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\common\gc_sync_ffs.vhd".
|
|
g_sync_edge = "positive"
|
|
Register <synced_o> equivalent to <sync2> has been removed
|
|
Found 1-bit register for signal <sync1>.
|
|
Found 1-bit register for signal <sync2>.
|
|
Found 1-bit register for signal <npulse_o>.
|
|
Found 1-bit register for signal <ppulse_o>.
|
|
Found 1-bit register for signal <sync0>.
|
|
Summary:
|
|
inferred 5 D-type flip-flop(s).
|
|
Unit <gc_sync_ffs> synthesized.
|
|
|
|
Synthesizing Unit <xwb_i2c_master>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\xwb_i2c_master.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <slave_o_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <slave_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_i2c_master> synthesized.
|
|
|
|
Synthesizing Unit <wb_i2c_master>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\wb_i2c_master.vhd" line 98: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_i2c_master> synthesized.
|
|
|
|
Synthesizing Unit <i2c_master_top>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_top.vhd".
|
|
ARST_LVL = '0'
|
|
WARNING:Xst:647 - Input <arst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 16-bit register for signal <prer>.
|
|
Found 8-bit register for signal <ctr>.
|
|
Found 8-bit register for signal <txr>.
|
|
Found 8-bit register for signal <cr>.
|
|
Found 1-bit register for signal <al>.
|
|
Found 1-bit register for signal <rxack>.
|
|
Found 1-bit register for signal <tip>.
|
|
Found 1-bit register for signal <irq_flag>.
|
|
Found 1-bit register for signal <wb_inta_o>.
|
|
Found 8-bit register for signal <wb_dat_o>.
|
|
Found 1-bit register for signal <iack_o>.
|
|
Found 8-bit 8-to-1 multiplexer for signal <wb_adr_i[2]_GND_122_o_wide_mux_0_OUT> created at line 191.
|
|
Summary:
|
|
inferred 54 D-type flip-flop(s).
|
|
inferred 16 Multiplexer(s).
|
|
Unit <i2c_master_top> synthesized.
|
|
|
|
Synthesizing Unit <i2c_master_byte_ctrl>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_byte_ctrl.vhd".
|
|
Found 3-bit register for signal <dcnt>.
|
|
Found 3-bit register for signal <c_state>.
|
|
Found 4-bit register for signal <core_cmd>.
|
|
Found 8-bit register for signal <sr>.
|
|
Found 1-bit register for signal <core_txd>.
|
|
Found 1-bit register for signal <shift>.
|
|
Found 1-bit register for signal <ld>.
|
|
Found 1-bit register for signal <host_ack>.
|
|
Found 1-bit register for signal <ack_out>.
|
|
Found finite state machine <FSM_5> for signal <c_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 6 |
|
|
| Transitions | 26 |
|
|
| Inputs | 9 |
|
|
| Outputs | 3 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | nReset (negative) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | st_idle |
|
|
| Power Up State | st_idle |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 3-bit subtractor for signal <GND_123_o_GND_123_o_sub_6_OUT<2:0>> created at line 1308.
|
|
Found 4-bit 6-to-1 multiplexer for signal <c_state[2]_X_74_o_wide_mux_38_OUT> created at line 264.
|
|
Found 1-bit 3-to-1 multiplexer for signal <c_state[1]_GND_123_o_Mux_40_o> created at line 264.
|
|
Found 1-bit 3-to-1 multiplexer for signal <c_state[2]_core_ack_Mux_42_o> created at line 264.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 20 D-type flip-flop(s).
|
|
inferred 34 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <i2c_master_byte_ctrl> synthesized.
|
|
|
|
Synthesizing Unit <i2c_master_bit_ctrl>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_i2c_master\i2c_master_bit_ctrl.vhd".
|
|
Found 3-bit register for signal <bus_status_ctrl.fSCL>.
|
|
Found 3-bit register for signal <bus_status_ctrl.fSDA>.
|
|
Found 16-bit register for signal <cnt>.
|
|
Found 2-bit register for signal <bus_status_ctrl.cSCL>.
|
|
Found 2-bit register for signal <bus_status_ctrl.cSDA>.
|
|
Found 14-bit register for signal <bus_status_ctrl.filter_cnt>.
|
|
Found 5-bit register for signal <c_state>.
|
|
Found 1-bit register for signal <slave_wait>.
|
|
Found 1-bit register for signal <bus_status_ctrl.sta_condition>.
|
|
Found 1-bit register for signal <bus_status_ctrl.sto_condition>.
|
|
Found 1-bit register for signal <bus_status_ctrl.ibusy>.
|
|
Found 1-bit register for signal <bus_status_ctrl.cmd_stop>.
|
|
Found 1-bit register for signal <ial>.
|
|
Found 1-bit register for signal <dout>.
|
|
Found 1-bit register for signal <cmd_ack>.
|
|
Found 1-bit register for signal <sda_chk>.
|
|
Found 1-bit register for signal <dscl_oen>.
|
|
Found 1-bit register for signal <sSCL>.
|
|
Found 1-bit register for signal <sSDA>.
|
|
Found 1-bit register for signal <dSCL>.
|
|
Found 1-bit register for signal <dSDA>.
|
|
Found 1-bit register for signal <iscl_oen>.
|
|
Found 1-bit register for signal <isda_oen>.
|
|
Found 1-bit register for signal <clk_en>.
|
|
Found finite state machine <FSM_6> for signal <c_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 18 |
|
|
| Transitions | 64 |
|
|
| Inputs | 6 |
|
|
| Outputs | 11 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | nReset (negative) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | idle |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit subtractor for signal <GND_124_o_GND_124_o_sub_2_OUT<15:0>> created at line 1308.
|
|
Found 14-bit subtractor for signal <GND_124_o_GND_124_o_sub_11_OUT<13:0>> created at line 1308.
|
|
Summary:
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 57 D-type flip-flop(s).
|
|
inferred 26 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <i2c_master_bit_ctrl> synthesized.
|
|
|
|
Synthesizing Unit <tri_state>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
Found 1-bit tristate buffer for signal <o> created at line 141
|
|
Summary:
|
|
inferred 1 Tristate(s).
|
|
Unit <tri_state> synthesized.
|
|
|
|
Synthesizing Unit <xwb_date_rev_id>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\xwb_date_rev_id.vhd".
|
|
g_interface_mode = classic
|
|
g_address_granularity = word
|
|
g_date_id = 0
|
|
g_revision_id = 0
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_date_rev_id> synthesized.
|
|
|
|
Synthesizing Unit <wb_date_rev_id>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd".
|
|
g_interface_mode = classic
|
|
g_address_granularity = word
|
|
g_date_id = 0
|
|
g_revision_id = 0
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <master_o_adr> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <master_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_date_rev_id\wb_date_rev_id.vhd" line 97: Output port <master_o_we> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
Found 1-bit register for signal <ack_int>.
|
|
Summary:
|
|
inferred 1 D-type flip-flop(s).
|
|
Unit <wb_date_rev_id> synthesized.
|
|
|
|
Synthesizing Unit <wb_slave_adapter_4>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd".
|
|
g_master_use_struct = true
|
|
g_master_mode = classic
|
|
g_master_granularity = word
|
|
g_slave_use_struct = false
|
|
g_slave_mode = classic
|
|
g_slave_granularity = word
|
|
WARNING:Xst:647 - Input <slave_i_adr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_slave_adapter_4> synthesized.
|
|
|
|
Synthesizing Unit <xwb_spi>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\xwb_spi.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <slave_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_spi> synthesized.
|
|
|
|
Synthesizing Unit <wb_spi>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\wb_spi.vhd" line 70: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_spi> synthesized.
|
|
|
|
Synthesizing Unit <wb_slave_adapter_5>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_slave_adapter.vhd".
|
|
g_master_use_struct = true
|
|
g_master_mode = classic
|
|
g_master_granularity = byte
|
|
g_slave_use_struct = false
|
|
g_slave_mode = pipelined
|
|
g_slave_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <master_i_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 1-bit register for signal <stored_we>.
|
|
Found 1-bit register for signal <fsm_state>.
|
|
Summary:
|
|
inferred 2 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
Unit <wb_slave_adapter_5> synthesized.
|
|
|
|
Synthesizing Unit <spi_top>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_top.v".
|
|
Tp = 1
|
|
WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 16-bit register for signal <divider>.
|
|
Found 8-bit register for signal <ss>.
|
|
Found 32-bit register for signal <wb_dat_o>.
|
|
Found 1-bit register for signal <wb_ack_o>.
|
|
Found 1-bit register for signal <wb_int_o>.
|
|
Found 1-bit register for signal <ctrl<13>>.
|
|
Found 1-bit register for signal <ctrl<12>>.
|
|
Found 1-bit register for signal <ctrl<11>>.
|
|
Found 1-bit register for signal <ctrl<10>>.
|
|
Found 1-bit register for signal <ctrl<9>>.
|
|
Found 1-bit register for signal <ctrl<8>>.
|
|
Found 1-bit register for signal <ctrl<7>>.
|
|
Found 1-bit register for signal <ctrl<6>>.
|
|
Found 1-bit register for signal <ctrl<5>>.
|
|
Found 1-bit register for signal <ctrl<4>>.
|
|
Found 1-bit register for signal <ctrl<3>>.
|
|
Found 1-bit register for signal <ctrl<2>>.
|
|
Found 1-bit register for signal <ctrl<1>>.
|
|
Found 1-bit register for signal <ctrl<0>>.
|
|
Found 32-bit 7-to-1 multiplexer for signal <wb_dat> created at line 115.
|
|
Summary:
|
|
inferred 72 D-type flip-flop(s).
|
|
inferred 18 Multiplexer(s).
|
|
Unit <spi_top> synthesized.
|
|
|
|
Synthesizing Unit <spi_clgen>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_clgen.v".
|
|
Tp = 1
|
|
Found 16-bit register for signal <cnt>.
|
|
Found 1-bit register for signal <clk_out>.
|
|
Found 1-bit register for signal <pos_edge>.
|
|
Found 1-bit register for signal <neg_edge>.
|
|
Found 16-bit subtractor for signal <cnt[15]_GND_148_o_sub_3_OUT> created at line 80.
|
|
Summary:
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 19 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
Unit <spi_clgen> synthesized.
|
|
|
|
Synthesizing Unit <spi_shift>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\WRPC\ip_cores\general-cores\modules\wishbone\wb_spi\spi_shift.v".
|
|
Tp = 1
|
|
Found 8-bit register for signal <cnt>.
|
|
Found 1-bit register for signal <tip>.
|
|
Found 1-bit register for signal <s_out>.
|
|
Found 1-bit register for signal <data<127>>.
|
|
Found 1-bit register for signal <data<126>>.
|
|
Found 1-bit register for signal <data<125>>.
|
|
Found 1-bit register for signal <data<124>>.
|
|
Found 1-bit register for signal <data<123>>.
|
|
Found 1-bit register for signal <data<122>>.
|
|
Found 1-bit register for signal <data<121>>.
|
|
Found 1-bit register for signal <data<120>>.
|
|
Found 1-bit register for signal <data<119>>.
|
|
Found 1-bit register for signal <data<118>>.
|
|
Found 1-bit register for signal <data<117>>.
|
|
Found 1-bit register for signal <data<116>>.
|
|
Found 1-bit register for signal <data<115>>.
|
|
Found 1-bit register for signal <data<114>>.
|
|
Found 1-bit register for signal <data<113>>.
|
|
Found 1-bit register for signal <data<112>>.
|
|
Found 1-bit register for signal <data<111>>.
|
|
Found 1-bit register for signal <data<110>>.
|
|
Found 1-bit register for signal <data<109>>.
|
|
Found 1-bit register for signal <data<108>>.
|
|
Found 1-bit register for signal <data<107>>.
|
|
Found 1-bit register for signal <data<106>>.
|
|
Found 1-bit register for signal <data<105>>.
|
|
Found 1-bit register for signal <data<104>>.
|
|
Found 1-bit register for signal <data<103>>.
|
|
Found 1-bit register for signal <data<102>>.
|
|
Found 1-bit register for signal <data<101>>.
|
|
Found 1-bit register for signal <data<100>>.
|
|
Found 1-bit register for signal <data<99>>.
|
|
Found 1-bit register for signal <data<98>>.
|
|
Found 1-bit register for signal <data<97>>.
|
|
Found 1-bit register for signal <data<96>>.
|
|
Found 1-bit register for signal <data<95>>.
|
|
Found 1-bit register for signal <data<94>>.
|
|
Found 1-bit register for signal <data<93>>.
|
|
Found 1-bit register for signal <data<92>>.
|
|
Found 1-bit register for signal <data<91>>.
|
|
Found 1-bit register for signal <data<90>>.
|
|
Found 1-bit register for signal <data<89>>.
|
|
Found 1-bit register for signal <data<88>>.
|
|
Found 1-bit register for signal <data<87>>.
|
|
Found 1-bit register for signal <data<86>>.
|
|
Found 1-bit register for signal <data<85>>.
|
|
Found 1-bit register for signal <data<84>>.
|
|
Found 1-bit register for signal <data<83>>.
|
|
Found 1-bit register for signal <data<82>>.
|
|
Found 1-bit register for signal <data<81>>.
|
|
Found 1-bit register for signal <data<80>>.
|
|
Found 1-bit register for signal <data<79>>.
|
|
Found 1-bit register for signal <data<78>>.
|
|
Found 1-bit register for signal <data<77>>.
|
|
Found 1-bit register for signal <data<76>>.
|
|
Found 1-bit register for signal <data<75>>.
|
|
Found 1-bit register for signal <data<74>>.
|
|
Found 1-bit register for signal <data<73>>.
|
|
Found 1-bit register for signal <data<72>>.
|
|
Found 1-bit register for signal <data<71>>.
|
|
Found 1-bit register for signal <data<70>>.
|
|
Found 1-bit register for signal <data<69>>.
|
|
Found 1-bit register for signal <data<68>>.
|
|
Found 1-bit register for signal <data<67>>.
|
|
Found 1-bit register for signal <data<66>>.
|
|
Found 1-bit register for signal <data<65>>.
|
|
Found 1-bit register for signal <data<64>>.
|
|
Found 1-bit register for signal <data<63>>.
|
|
Found 1-bit register for signal <data<62>>.
|
|
Found 1-bit register for signal <data<61>>.
|
|
Found 1-bit register for signal <data<60>>.
|
|
Found 1-bit register for signal <data<59>>.
|
|
Found 1-bit register for signal <data<58>>.
|
|
Found 1-bit register for signal <data<57>>.
|
|
Found 1-bit register for signal <data<56>>.
|
|
Found 1-bit register for signal <data<55>>.
|
|
Found 1-bit register for signal <data<54>>.
|
|
Found 1-bit register for signal <data<53>>.
|
|
Found 1-bit register for signal <data<52>>.
|
|
Found 1-bit register for signal <data<51>>.
|
|
Found 1-bit register for signal <data<50>>.
|
|
Found 1-bit register for signal <data<49>>.
|
|
Found 1-bit register for signal <data<48>>.
|
|
Found 1-bit register for signal <data<47>>.
|
|
Found 1-bit register for signal <data<46>>.
|
|
Found 1-bit register for signal <data<45>>.
|
|
Found 1-bit register for signal <data<44>>.
|
|
Found 1-bit register for signal <data<43>>.
|
|
Found 1-bit register for signal <data<42>>.
|
|
Found 1-bit register for signal <data<41>>.
|
|
Found 1-bit register for signal <data<40>>.
|
|
Found 1-bit register for signal <data<39>>.
|
|
Found 1-bit register for signal <data<38>>.
|
|
Found 1-bit register for signal <data<37>>.
|
|
Found 1-bit register for signal <data<36>>.
|
|
Found 1-bit register for signal <data<35>>.
|
|
Found 1-bit register for signal <data<34>>.
|
|
Found 1-bit register for signal <data<33>>.
|
|
Found 1-bit register for signal <data<32>>.
|
|
Found 1-bit register for signal <data<31>>.
|
|
Found 1-bit register for signal <data<30>>.
|
|
Found 1-bit register for signal <data<29>>.
|
|
Found 1-bit register for signal <data<28>>.
|
|
Found 1-bit register for signal <data<27>>.
|
|
Found 1-bit register for signal <data<26>>.
|
|
Found 1-bit register for signal <data<25>>.
|
|
Found 1-bit register for signal <data<24>>.
|
|
Found 1-bit register for signal <data<23>>.
|
|
Found 1-bit register for signal <data<22>>.
|
|
Found 1-bit register for signal <data<21>>.
|
|
Found 1-bit register for signal <data<20>>.
|
|
Found 1-bit register for signal <data<19>>.
|
|
Found 1-bit register for signal <data<18>>.
|
|
Found 1-bit register for signal <data<17>>.
|
|
Found 1-bit register for signal <data<16>>.
|
|
Found 1-bit register for signal <data<15>>.
|
|
Found 1-bit register for signal <data<14>>.
|
|
Found 1-bit register for signal <data<13>>.
|
|
Found 1-bit register for signal <data<12>>.
|
|
Found 1-bit register for signal <data<11>>.
|
|
Found 1-bit register for signal <data<10>>.
|
|
Found 1-bit register for signal <data<9>>.
|
|
Found 1-bit register for signal <data<8>>.
|
|
Found 1-bit register for signal <data<7>>.
|
|
Found 1-bit register for signal <data<6>>.
|
|
Found 1-bit register for signal <data<5>>.
|
|
Found 1-bit register for signal <data<4>>.
|
|
Found 1-bit register for signal <data<3>>.
|
|
Found 1-bit register for signal <data<2>>.
|
|
Found 1-bit register for signal <data<1>>.
|
|
Found 1-bit register for signal <data<0>>.
|
|
Found 8-bit subtractor for signal <len[6]_cnt[7]_sub_3_OUT> created at line 82.
|
|
Found 8-bit subtractor for signal <cnt[7]_GND_150_o_sub_4_OUT> created at line 82.
|
|
Found 8-bit subtractor for signal <len[6]_cnt[7]_sub_9_OUT> created at line 83.
|
|
Found 8-bit adder for signal <cnt[7]_GND_150_o_add_6_OUT> created at line 83.
|
|
Found 1-bit 128-to-1 multiplexer for signal <tx_bit_pos[6]_data[127]_Mux_19_o> created at line 122.
|
|
Found 1-bit 128-to-1 multiplexer for signal <rx_bit_pos[6]_data[127]_Mux_20_o> created at line 234.
|
|
Summary:
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 138 D-type flip-flop(s).
|
|
inferred 141 Multiplexer(s).
|
|
Unit <spi_shift> synthesized.
|
|
|
|
Synthesizing Unit <xwb_tdc>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\xwb_tdc.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
c_tdc_channels = 3
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\xwb_tdc.vhd" line 74: Output port <wb_int_o> of the instance <U_Wrapped_tdc> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_tdc> synthesized.
|
|
|
|
Synthesizing Unit <wb_tdc_master>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
c_tdc_channels = 3
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wb_tdc.vhd" line 80: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_tdc_master> synthesized.
|
|
|
|
Synthesizing Unit <tdc_master_top>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\wrapped_mux_tdc.vhd".
|
|
ARST_LVL = '0'
|
|
c_tdc_channels = 3
|
|
WARNING:Xst:647 - Input <arst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <wb_inta_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 32-bit register for signal <rtdc0>.
|
|
Found 32-bit register for signal <rtdc1>.
|
|
Found 32-bit register for signal <rtdc2>.
|
|
Found 32-bit register for signal <wb_dat_o>.
|
|
Found 1-bit register for signal <iack_o>.
|
|
Found 32-bit 5-to-1 multiplexer for signal <wb_adr_i[2]_X_89_o_wide_mux_0_OUT> created at line 131.
|
|
Summary:
|
|
inferred 129 D-type flip-flop(s).
|
|
inferred 4 Multiplexer(s).
|
|
Unit <tdc_master_top> synthesized.
|
|
|
|
Synthesizing Unit <mux_tdc>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd".
|
|
timeslice_duration = 1
|
|
freq_clock = 250
|
|
c_tdc_channels = 3
|
|
bytes_datagram = 900
|
|
WARNING:Xst:647 - Input <rtdc0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rtdc1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rtdc2<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rtdc2<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <S<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <S_N<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 233: Output port <LOCKED> of the instance <dcm250> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 246: Output port <CLK_OUT3> of the instance <dcm2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 246: Output port <CLK_OUT4> of the instance <dcm2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 246: Output port <LOCKED> of the instance <dcm2> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 256: Output port <rx_data> of the instance <u> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 256: Output port <rx_ready> of the instance <u> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 270: Output port <data_counter> of the instance <all_channels[2].channel_tdc> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 270: Output port <S_O> of the instance <all_channels[2].channel_tdc> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 270: Output port <S_O> of the instance <all_channels[1].channel_tdc> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mux_tdc.vhd" line 270: Output port <S_O> of the instance <all_channels[0].channel_tdc> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <rtdc3<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <rtdc4<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 32-bit register for signal <n_time_slice>.
|
|
Found 32-bit register for signal <channel>.
|
|
Found 2-bit register for signal <state_ts>.
|
|
Found 2-bit register for signal <n_state>.
|
|
Found 32-bit register for signal <index_ch>.
|
|
Found 32-bit register for signal <i_index>.
|
|
Found 28-bit register for signal <duration>.
|
|
Found 3-bit register for signal <state_down>.
|
|
Found 1-bit register for signal <new_time_slice>.
|
|
Found 1-bit register for signal <enable_download>.
|
|
Found 1-bit register for signal <word_ready>.
|
|
Found 1-bit register for signal <tx_en>.
|
|
Found 1-bit register for signal <tx_word_end>.
|
|
Found 3-bit register for signal <download>.
|
|
Found 16-bit register for signal <word>.
|
|
Found 8-bit register for signal <tx_data>.
|
|
Found finite state machine <FSM_7> for signal <state_ts>.
|
|
-----------------------------------------------------------------------
|
|
| States | 2 |
|
|
| Transitions | 5 |
|
|
| Inputs | 2 |
|
|
| Outputs | 1 |
|
|
| Clock | clk_0 (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | 00 |
|
|
| Power Up State | 00 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found finite state machine <FSM_8> for signal <n_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 13 |
|
|
| Inputs | 3 |
|
|
| Outputs | 2 |
|
|
| Clock | clk_0 (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | 00 |
|
|
| Power Up State | 00 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found finite state machine <FSM_9> for signal <state_down>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 20 |
|
|
| Inputs | 6 |
|
|
| Outputs | 4 |
|
|
| Clock | clk_0 (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | header |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 28-bit adder for signal <duration[27]_GND_161_o_add_4_OUT> created at line 314.
|
|
Found 32-bit adder for signal <n_time_slice[31]_GND_161_o_add_6_OUT> created at line 319.
|
|
Found 32-bit adder for signal <channel[31]_GND_161_o_add_87_OUT> created at line 404.
|
|
Found 32-bit subtractor for signal <i_index[31]_GND_161_o_sub_86_OUT<31:0>> created at line 398.
|
|
Found 48-bit 3-to-1 multiplexer for signal <n0161> created at line 382.
|
|
Found 1-bit 3-to-1 multiplexer for signal <channel[1]_X_91_o_Mux_27_o> created at line 382.
|
|
Found 28-bit comparator greater for signal <duration[27]_GND_161_o_LessThan_4_o> created at line 313
|
|
Found 32-bit comparator greater for signal <GND_161_o_n_time_slice[31]_LessThan_6_o> created at line 316
|
|
Found 32-bit comparator greater for signal <i_index[31]_GND_161_o_LessThan_85_o> created at line 397
|
|
Found 32-bit comparator greater for signal <GND_161_o_channel[31]_LessThan_87_o> created at line 403
|
|
Summary:
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 188 D-type flip-flop(s).
|
|
inferred 4 Comparator(s).
|
|
inferred 50 Multiplexer(s).
|
|
inferred 3 Finite State Machine(s).
|
|
Unit <mux_tdc> synthesized.
|
|
|
|
Synthesizing Unit <dcm_tdc_250>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\dcm_tdc_250.vhd".
|
|
Summary:
|
|
no macro.
|
|
Unit <dcm_tdc_250> synthesized.
|
|
|
|
Synthesizing Unit <mydcm_phases>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\mydcm_phases.vhd".
|
|
Summary:
|
|
no macro.
|
|
Unit <mydcm_phases> synthesized.
|
|
|
|
Synthesizing Unit <uart>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\uart232.vhd".
|
|
CLK_FREQ = 250
|
|
SER_FREQ = 921600
|
|
Found 9-bit register for signal <tx_clk_gen.counter>.
|
|
Found 1-bit register for signal <tx_end>.
|
|
Found 1-bit register for signal <tx>.
|
|
Found 8-bit register for signal <tx_data_tmp>.
|
|
Found 3-bit register for signal <tx_fsm>.
|
|
Found 3-bit register for signal <tx_data_cnt>.
|
|
Found 1-bit register for signal <tx_par_bit>.
|
|
Found 1-bit register for signal <rx_data_deb>.
|
|
Found 4-bit register for signal <rx_debounceer.deb_buf>.
|
|
Found 1-bit register for signal <rx_rcv_init>.
|
|
Found 1-bit register for signal <rx_start_detect.rx_data_old>.
|
|
Found 1-bit register for signal <rx_clk_en>.
|
|
Found 9-bit register for signal <rx_clk_gen.counter>.
|
|
Found 1-bit register for signal <rx_ready>.
|
|
Found 3-bit register for signal <rx_fsm>.
|
|
Found 1-bit register for signal <rx_par_bit>.
|
|
Found 3-bit register for signal <rx_data_cnt>.
|
|
Found 8-bit register for signal <rx_data>.
|
|
Found 8-bit register for signal <rx_data_tmp>.
|
|
Found 1-bit register for signal <tx_clk_en>.
|
|
Found finite state machine <FSM_10> for signal <tx_fsm>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 12 |
|
|
| Inputs | 3 |
|
|
| Outputs | 3 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | _n0174 (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | idle |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
INFO:Xst:1799 - State stop1 is never reached in FSM <rx_fsm>.
|
|
INFO:Xst:1799 - State stop2 is never reached in FSM <rx_fsm>.
|
|
Found finite state machine <FSM_11> for signal <rx_fsm>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 11 |
|
|
| Inputs | 4 |
|
|
| Outputs | 3 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | _n0183 (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | idle |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 9-bit adder for signal <tx_clk_gen.counter[8]_GND_228_o_add_1_OUT> created at line 78.
|
|
Found 9-bit adder for signal <rx_clk_gen.counter[8]_GND_228_o_add_33_OUT> created at line 196.
|
|
Found 3-bit adder for signal <rx_data_cnt[2]_GND_228_o_add_40_OUT> created at line 246.
|
|
Found 3-bit subtractor for signal <GND_228_o_GND_228_o_sub_11_OUT<2:0>> created at line 121.
|
|
Summary:
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 62 D-type flip-flop(s).
|
|
inferred 15 Multiplexer(s).
|
|
inferred 2 Finite State Machine(s).
|
|
Unit <uart> synthesized.
|
|
|
|
Synthesizing Unit <tdc_top>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd".
|
|
WARNING:Xst:647 - Input <sw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" line 198: Output port <wr_data_count> of the instance <c_fifo_tdc> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\tdc_top.vhd" line 198: Output port <full> of the instance <c_fifo_tdc> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <SYNC_OUT> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <tdc_top> synthesized.
|
|
|
|
Synthesizing Unit <DRU>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone\wb_tdc\DRU.vhd".
|
|
Found 32-bit register for signal <count_ts>.
|
|
Found 32-bit register for signal <d_out_ts>.
|
|
Found 32-bit register for signal <count_rem>.
|
|
Found 9-bit register for signal <count>.
|
|
Found 2-bit register for signal <p_state>.
|
|
Found 1-bit register for signal <enable_ts>.
|
|
Found 1-bit register for signal <n_d>.
|
|
Found 1-bit register for signal <flag_rem>.
|
|
Found 40-bit register for signal <d_out>.
|
|
Found finite state machine <FSM_12> for signal <p_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 15 |
|
|
| Inputs | 7 |
|
|
| Outputs | 3 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | 00 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 32-bit adder for signal <count_ts[31]_GND_232_o_add_3_OUT> created at line 67.
|
|
Found 9-bit adder for signal <count[8]_GND_232_o_add_30_OUT> created at line 84.
|
|
Found 32-bit adder for signal <count_rem[31]_GND_232_o_add_35_OUT> created at line 89.
|
|
Found 32-bit subtractor for signal <GND_232_o_GND_232_o_sub_52_OUT<31:0>> created at line 108.
|
|
Found 9-bit adder for signal <_n0280> created at line 75.
|
|
Found 9-bit adder for signal <_n0281> created at line 75.
|
|
Found 9-bit adder for signal <_n0282> created at line 75.
|
|
Found 9-bit adder for signal <count[8]_GND_232_o_add_9_OUT> created at line 75.
|
|
Found 8-bit adder for signal <_n0284> created at line 88.
|
|
Found 8-bit adder for signal <_n0285> created at line 88.
|
|
Found 8-bit adder for signal <_n0286> created at line 88.
|
|
Found 8-bit adder for signal <count[7]_GND_232_o_add_34_OUT> created at line 88.
|
|
Found 32-bit adder for signal <_n0288> created at line 89.
|
|
Found 32-bit adder for signal <_n0289> created at line 89.
|
|
Found 32-bit adder for signal <_n0290> created at line 89.
|
|
Found 32-bit subtractor for signal <GND_232_o_GND_232_o_sub_40_OUT<31:0>> created at line 89.
|
|
Found 32-bit adder for signal <_n0298> created at line 76.
|
|
Found 32-bit adder for signal <_n0299> created at line 76.
|
|
Found 32-bit subtractor for signal <GND_232_o_GND_232_o_sub_55_OUT<31:0>> created at line 76.
|
|
Found 32-bit adder for signal <_n0304> created at line 76.
|
|
Found 32-bit adder for signal <GND_232_o_GND_232_o_sub_16_OUT<31:0>> created at line 76.
|
|
Found 1-bit 4-to-1 multiplexer for signal <p_state[1]_PWR_108_o_Mux_65_o> created at line 54.
|
|
Found 32-bit comparator greater for signal <count_ts[31]_PWR_108_o_LessThan_3_o> created at line 66
|
|
Summary:
|
|
inferred 21 Adder/Subtractor(s).
|
|
inferred 148 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
inferred 15 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <DRU> synthesized.
|
|
|
|
Synthesizing Unit <xwb_multiboot>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\xwb_multiboot.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\xwb_multiboot.vhd" line 60: Output port <wb_int_o> of the instance <U_multiboot> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_multiboot> synthesized.
|
|
|
|
Synthesizing Unit <wb_multiboot>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
INFO:Xst:3210 - "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\wb_multiboot.vhd" line 73: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
|
|
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <wb_multiboot> synthesized.
|
|
|
|
Synthesizing Unit <multiboot_master_top>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot_master_top.vhd".
|
|
ARST_LVL = '0'
|
|
WARNING:Xst:647 - Input <arst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <wb_inta_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Found 32-bit register for signal <rmb0>.
|
|
Found 32-bit register for signal <rmb1>.
|
|
Found 32-bit register for signal <wb_dat_o>.
|
|
Found 1-bit register for signal <iack_o>.
|
|
Summary:
|
|
inferred 97 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
Unit <multiboot_master_top> synthesized.
|
|
|
|
Synthesizing Unit <multiboot>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\TestDesigns\multiboot\wb\multiboot.vhd".
|
|
WARNING:Xst:647 - Input <rmb1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 1-bit register for signal <CE>.
|
|
Found 1-bit register for signal <ICAP_WRITE>.
|
|
Found 32-bit register for signal <I>.
|
|
Found 4-bit register for signal <NEXT_STATE>.
|
|
Found finite state machine <FSM_13> for signal <NEXT_STATE>.
|
|
-----------------------------------------------------------------------
|
|
| States | 12 |
|
|
| Transitions | 24 |
|
|
| Inputs | 1 |
|
|
| Outputs | 34 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | state_00 |
|
|
| Power Up State | state_00 |
|
|
| Encoding | auto |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Summary:
|
|
inferred 34 D-type flip-flop(s).
|
|
inferred 3 Multiplexer(s).
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <multiboot> synthesized.
|
|
|
|
Synthesizing Unit <xwb_aes>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\modules\xwb_aes_empty.vhd".
|
|
g_interface_mode = pipelined
|
|
g_address_granularity = byte
|
|
g_word_size = 64
|
|
WARNING:Xst:647 - Input <slave_i_adr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_dat> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <aes_i_audio_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <aes_i_fifo_rd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <aes_o_fifo_dout> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <aes_o_fifo_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
WARNING:Xst:653 - Signal <aes_o_fifo_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
|
|
Summary:
|
|
no macro.
|
|
Unit <xwb_aes> synthesized.
|
|
|
|
Synthesizing Unit <cmp_sys_clk_pll>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\ip_cores\cmp_sys_clk_pll.vhd".
|
|
Summary:
|
|
no macro.
|
|
Unit <cmp_sys_clk_pll> synthesized.
|
|
|
|
Synthesizing Unit <dummy_aes>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
Summary:
|
|
no macro.
|
|
Unit <dummy_aes> synthesized.
|
|
|
|
Synthesizing Unit <i_tdc>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
c_tdc_channels = 3
|
|
Summary:
|
|
no macro.
|
|
Unit <i_tdc> synthesized.
|
|
|
|
Synthesizing Unit <low>.
|
|
Related source file is "C:\David\proyectos_kintex\CLBv2\trunk\fw\CLBv2_Design\lm32_2nd\top\fpga.vhd".
|
|
n = 30
|
|
Summary:
|
|
no macro.
|
|
Unit <low> synthesized.
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 8
|
|
1024x32-bit dual-port RAM : 1
|
|
20480x32-bit dual-port RAM : 1
|
|
256x20-bit dual-port RAM : 1
|
|
32x32-bit dual-port RAM : 2
|
|
512x32-bit single-port Read Only RAM : 1
|
|
64x32-bit single-port Read Only RAM : 1
|
|
8x1-bit single-port Read Only RAM : 1
|
|
# Multipliers : 3
|
|
16x16-bit multiplier : 3
|
|
# Adders/Subtractors : 104
|
|
14-bit subtractor : 2
|
|
16-bit adder : 3
|
|
16-bit subtractor : 3
|
|
17-bit adder : 1
|
|
2-bit adder : 2
|
|
2-bit addsub : 1
|
|
2-bit subtractor : 1
|
|
24-bit adder : 1
|
|
28-bit adder : 1
|
|
29-bit adder : 2
|
|
3-bit adder : 1
|
|
3-bit subtractor : 4
|
|
32-bit adder : 33
|
|
32-bit subtractor : 10
|
|
33-bit adder : 2
|
|
33-bit subtractor : 2
|
|
4-bit adder : 1
|
|
8-bit adder : 13
|
|
8-bit subtractor : 4
|
|
9-bit adder : 17
|
|
# Registers : 589
|
|
1-bit register : 414
|
|
10-bit register : 1
|
|
11-bit register : 3
|
|
14-bit register : 2
|
|
16-bit register : 13
|
|
17-bit register : 1
|
|
18-bit register : 1
|
|
2-bit register : 10
|
|
23-bit register : 2
|
|
24-bit register : 1
|
|
28-bit register : 1
|
|
29-bit register : 9
|
|
3-bit register : 12
|
|
32-bit register : 60
|
|
4-bit register : 12
|
|
40-bit register : 3
|
|
5-bit register : 6
|
|
6-bit register : 1
|
|
8-bit register : 31
|
|
9-bit register : 6
|
|
# Comparators : 22
|
|
1-bit comparator equal : 1
|
|
20-bit comparator equal : 1
|
|
28-bit comparator greater : 1
|
|
32-bit comparator equal : 5
|
|
32-bit comparator greater : 6
|
|
5-bit comparator equal : 8
|
|
# Multiplexers : 806
|
|
1-bit 128-to-1 multiplexer : 2
|
|
1-bit 2-to-1 multiplexer : 486
|
|
1-bit 3-to-1 multiplexer : 5
|
|
1-bit 4-to-1 multiplexer : 35
|
|
1-bit 8-to-1 multiplexer : 2
|
|
11-bit 2-to-1 multiplexer : 2
|
|
14-bit 2-to-1 multiplexer : 4
|
|
16-bit 2-to-1 multiplexer : 39
|
|
18-bit 2-to-1 multiplexer : 1
|
|
2-bit 2-to-1 multiplexer : 8
|
|
23-bit 2-to-1 multiplexer : 2
|
|
24-bit 2-to-1 multiplexer : 1
|
|
28-bit 2-to-1 multiplexer : 3
|
|
29-bit 2-to-1 multiplexer : 7
|
|
3-bit 2-to-1 multiplexer : 19
|
|
32-bit 2-to-1 multiplexer : 95
|
|
32-bit 3-to-1 multiplexer : 3
|
|
32-bit 5-to-1 multiplexer : 1
|
|
32-bit 7-to-1 multiplexer : 1
|
|
4-bit 2-to-1 multiplexer : 25
|
|
4-bit 6-to-1 multiplexer : 2
|
|
40-bit 2-to-1 multiplexer : 6
|
|
48-bit 3-to-1 multiplexer : 1
|
|
5-bit 2-to-1 multiplexer : 4
|
|
8-bit 2-to-1 multiplexer : 35
|
|
8-bit 4-to-1 multiplexer : 1
|
|
8-bit 8-to-1 multiplexer : 2
|
|
9-bit 2-to-1 multiplexer : 14
|
|
# Logic shifters : 1
|
|
64-bit shifter logical right : 1
|
|
# Tristates : 5
|
|
1-bit tristate buffer : 4
|
|
7-bit tristate buffer : 1
|
|
# FSMs : 18
|
|
# Xors : 93
|
|
1-bit xor2 : 67
|
|
32-bit xor2 : 26
|
|
|
|
=========================================================================
|
|
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Reading core <../../ip_cores/fifo.ngc>.
|
|
Loading core <fifo> for timing and area information for instance <c_fifo_tdc>.
|
|
WARNING:Xst:1290 - Hierarchical block <u2> is unconnected in block <fpga>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u19> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u2> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u20> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u21> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u22> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u23> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u24> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u25> is unconnected in block <u0>.
|
|
It will be removed from the design.
|
|
WARNING:Xst:1290 - Hierarchical block <u9> is unconnected in block <fpga>.
|
|
It will be removed from the design.
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31>
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[4].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[3].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[2].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[1].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[5].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[0].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <sync0> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[6].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[0].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[5].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[1].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[2].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[4].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[6].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[3].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[5].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[4].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[6].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[3].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[2].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[1].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <GEN_SYNC_FFS[0].INPUT_SYNC>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <index_ch_31> of sequential type is unconnected in block <U_Mux_tdc>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <U_Wrapped_UART>.
|
|
WARNING:Xst:2404 - FFs/Latches <rx_data<7:7>> (without init value) have a constant value of 0 in block <uart>.
|
|
WARNING:Xst:2404 - FFs/Latches <ack_sreg<7:1>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
|
|
|
|
Synthesizing (advanced) Unit <Counter>.
|
|
The following registers are absorbed into counter <Count>: 1 register on signal <Count>.
|
|
Unit <Counter> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <DRU>.
|
|
The following adders/subtractors are grouped into adder tree <Madd_count[7]_GND_232_o_add_34_OUT1> :
|
|
<Madd_count[7]_GND_232_o_add_34_OUT> in block <DRU>, <Madd__n0285> in block <DRU>, <Madd__n0286_Madd> in block <DRU>.
|
|
Unit <DRU> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <generic_dpram_sameclock>.
|
|
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 20480-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkA | connected to signal <clk_i> | rise |
|
|
| weA<3> | connected to signal <s_we_a<3>> | high |
|
|
| weA<2> | connected to signal <s_we_a<2>> | high |
|
|
| weA<1> | connected to signal <s_we_a<1>> | high |
|
|
| weA<0> | connected to signal <s_we_a<0>> | high |
|
|
| addrA | connected to signal <aa_i> | |
|
|
| diA | connected to signal <da_i> | |
|
|
| doA | connected to signal <qa_o> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 20480-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clk_i> | rise |
|
|
| weB<3> | connected to signal <s_we_b<3>> | high |
|
|
| weB<2> | connected to signal <s_we_b<2>> | high |
|
|
| weB<1> | connected to signal <s_we_b<1>> | high |
|
|
| weB<0> | connected to signal <s_we_b<0>> | high |
|
|
| addrB | connected to signal <ab_i> | |
|
|
| diB | connected to signal <db_i> | |
|
|
| doB | connected to signal <qb_o> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <generic_dpram_sameclock> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <i2c_master_bit_ctrl>.
|
|
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
|
|
Unit <i2c_master_bit_ctrl> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <lm32_cpu_medium_icache_debug>.
|
|
INFO:Xst:3226 - The RAM <reg_0/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_0/raddr_r>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkA | connected to signal <clk_i> | rise |
|
|
| weA | connected to signal <reg_write_enable_q_w> | high |
|
|
| addrA | connected to signal <write_idx_w> | |
|
|
| diA | connected to signal <w_result> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clk_i> | rise |
|
|
| addrB | connected to signal <instruction_f<25:21>> | |
|
|
| doB | connected to signal <regfile_data_0> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
INFO:Xst:3226 - The RAM <reg_1/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_1/raddr_r>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkA | connected to signal <clk_i> | rise |
|
|
| weA | connected to signal <reg_write_enable_q_w> | high |
|
|
| addrA | connected to signal <write_idx_w> | |
|
|
| diA | connected to signal <w_result> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clk_i> | rise |
|
|
| addrB | connected to signal <instruction_f<20:16>> | |
|
|
| doB | connected to signal <regfile_data_1> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <lm32_cpu_medium_icache_debug> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <lm32_icache_medium_icache_debug>.
|
|
The following registers are absorbed into counter <flush_set>: 1 register on signal <flush_set>.
|
|
INFO:Xst:3226 - The RAM <memories[0].way_0_data_ram/Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <memories[0].way_0_data_ram/ra>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 1024-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkA | connected to signal <clk_i> | rise |
|
|
| weA | connected to signal <way_mem_we> | high |
|
|
| addrA | connected to signal <(refill_address<11:4>,refill_offset)> | |
|
|
| diA | connected to signal <refill_data> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 1024-word x 32-bit | |
|
|
| mode | write-first | |
|
|
| clkB | connected to signal <clk_i> | rise |
|
|
| addrB | connected to signal <address_a> | |
|
|
| doB | connected to signal <way_data<0>> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <lm32_icache_medium_icache_debug> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <lm32_multiplier>.
|
|
Multiplier <Mmult_n0056> in block <lm32_multiplier> and adder/subtractor <Madd_c1[15]_e1[15]_add_17_OUT> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0056>.
|
|
The following registers are also absorbed by the MAC: <e1> in block <lm32_multiplier>, <result1,result0> in block <lm32_multiplier>.
|
|
Multiplier <Mmult_n0055> in block <lm32_multiplier> and adder/subtractor <Madd_n0077> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0055>.
|
|
The following registers are also absorbed by the MAC: <d1> in block <lm32_multiplier>.
|
|
Found pipelined multiplier on signal <a0[15]_b0[15]_MuLt_9_OUT>:
|
|
- 1 pipeline level(s) found in a register connected to the multiplier macro output.
|
|
Pushing register(s) into the multiplier macro.
|
|
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s).
|
|
Unit <lm32_multiplier> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <lm32_ram_2>.
|
|
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 256-word x 20-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <write_clk> | rise |
|
|
| weA | connected to signal <write_enable> | high |
|
|
| addrA | connected to signal <write_address> | |
|
|
| diA | connected to signal <write_data> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 256-word x 20-bit | |
|
|
| mode | write-first | |
|
|
| clkB | connected to signal <read_clk> | rise |
|
|
| addrB | connected to signal <read_address> | |
|
|
| doB | connected to internal node | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <lm32_ram_2> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <mux_tdc>.
|
|
The following registers are absorbed into counter <n_time_slice>: 1 register on signal <n_time_slice>.
|
|
The following registers are absorbed into counter <channel>: 1 register on signal <channel>.
|
|
Unit <mux_tdc> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <sdb_rom_1>.
|
|
INFO:Xst:3231 - The small RAM <Mram_rom> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Distributed | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 64-word x 32-bit | |
|
|
| weA | connected to signal <GND> | high |
|
|
| addrA | connected to signal <adr_reg> | |
|
|
| diA | connected to signal <GND> | |
|
|
| doA | connected to internal node | |
|
|
-----------------------------------------------------------------------
|
|
Unit <sdb_rom_1> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <sdb_rom_2>.
|
|
INFO:Xst:3226 - The RAM <Mram_rom> will be implemented as a BLOCK RAM, absorbing the following register(s): <adr_reg>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 512-word x 32-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clk_sys_i> | rise |
|
|
| weA | connected to signal <GND> | high |
|
|
| addrA | connected to signal <slave_i_adr> | |
|
|
| diA | connected to signal <GND> | |
|
|
| doA | connected to internal node | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <sdb_rom_2> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <spi_clgen>.
|
|
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
|
|
Unit <spi_clgen> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <uart>.
|
|
The following registers are absorbed into counter <tx_clk_gen.counter>: 1 register on signal <tx_clk_gen.counter>.
|
|
The following registers are absorbed into counter <rx_data_cnt>: 1 register on signal <rx_data_cnt>.
|
|
The following registers are absorbed into counter <rx_clk_gen.counter>: 1 register on signal <rx_clk_gen.counter>.
|
|
Unit <uart> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <uart_async_rx>.
|
|
The following registers are absorbed into counter <RxD_cnt_inv>: 1 register on signal <RxD_cnt_inv>.
|
|
Unit <uart_async_rx> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <wb_gpio_port>.
|
|
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_write_mask<0>> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Distributed | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 8-word x 1-bit | |
|
|
| weA | connected to signal <GND> | high |
|
|
| addrA | connected to signal <wb_in_adr<5:3>> | |
|
|
| diA | connected to signal <GND> | |
|
|
| doA | connected to signal <write_mask> | |
|
|
-----------------------------------------------------------------------
|
|
Unit <wb_gpio_port> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <wb_tics>.
|
|
The following registers are absorbed into counter <cntr_tics>: 1 register on signal <cntr_tics>.
|
|
The following registers are absorbed into counter <cntr_div>: 1 register on signal <cntr_div>.
|
|
Unit <wb_tics> synthesized (advanced).
|
|
WARNING:Xst:2677 - Node <index_ch_31> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <rx_data_tmp_7> of sequential type is unconnected in block <uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <wb_simple_uart>.
|
|
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <wb_simple_uart>.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 8
|
|
1024x32-bit dual-port block RAM : 1
|
|
20480x32-bit dual-port block RAM : 1
|
|
256x20-bit dual-port block RAM : 1
|
|
32x32-bit dual-port block RAM : 2
|
|
512x32-bit single-port block Read Only RAM : 1
|
|
64x32-bit single-port distributed Read Only RAM : 1
|
|
8x1-bit single-port distributed Read Only RAM : 1
|
|
# MACs : 2
|
|
16x16-to-16-bit MAC : 2
|
|
# Multipliers : 1
|
|
16x16-bit registered multiplier : 1
|
|
# Adders/Subtractors : 66
|
|
1-bit subtractor : 1
|
|
14-bit subtractor : 2
|
|
16-bit adder : 1
|
|
17-bit adder : 1
|
|
2-bit adder : 2
|
|
28-bit adder : 1
|
|
29-bit adder : 2
|
|
3-bit subtractor : 4
|
|
32-bit adder : 20
|
|
32-bit adder carry in : 3
|
|
32-bit subtractor : 7
|
|
32-bit subtractor borrow in : 3
|
|
33-bit adder carry in : 1
|
|
33-bit subtractor borrow in : 1
|
|
4-bit adder : 1
|
|
7-bit subtractor : 2
|
|
8-bit adder : 1
|
|
8-bit subtractor : 1
|
|
9-bit adder : 9
|
|
9-bit adder carry in : 3
|
|
# Adder Trees : 3
|
|
8-bit / 4-inputs adder tree : 3
|
|
# Counters : 13
|
|
16-bit down counter : 3
|
|
2-bit updown counter : 1
|
|
24-bit up counter : 1
|
|
3-bit up counter : 1
|
|
32-bit up counter : 4
|
|
8-bit down counter : 1
|
|
9-bit up counter : 2
|
|
# Registers : 3150
|
|
Flip-Flops : 3150
|
|
# Comparators : 22
|
|
1-bit comparator equal : 1
|
|
20-bit comparator equal : 1
|
|
28-bit comparator greater : 1
|
|
32-bit comparator equal : 5
|
|
32-bit comparator greater : 6
|
|
5-bit comparator equal : 8
|
|
# Multiplexers : 1174
|
|
1-bit 128-to-1 multiplexer : 2
|
|
1-bit 2-to-1 multiplexer : 809
|
|
1-bit 3-to-1 multiplexer : 5
|
|
1-bit 4-to-1 multiplexer : 35
|
|
1-bit 5-to-1 multiplexer : 32
|
|
1-bit 7-to-1 multiplexer : 32
|
|
1-bit 8-to-1 multiplexer : 18
|
|
11-bit 2-to-1 multiplexer : 1
|
|
14-bit 2-to-1 multiplexer : 4
|
|
16-bit 2-to-1 multiplexer : 36
|
|
2-bit 2-to-1 multiplexer : 8
|
|
23-bit 2-to-1 multiplexer : 2
|
|
28-bit 2-to-1 multiplexer : 3
|
|
29-bit 2-to-1 multiplexer : 7
|
|
3-bit 2-to-1 multiplexer : 17
|
|
32-bit 2-to-1 multiplexer : 84
|
|
32-bit 3-to-1 multiplexer : 3
|
|
4-bit 2-to-1 multiplexer : 25
|
|
4-bit 6-to-1 multiplexer : 2
|
|
40-bit 2-to-1 multiplexer : 6
|
|
48-bit 3-to-1 multiplexer : 1
|
|
5-bit 2-to-1 multiplexer : 4
|
|
8-bit 2-to-1 multiplexer : 25
|
|
8-bit 4-to-1 multiplexer : 1
|
|
9-bit 2-to-1 multiplexer : 12
|
|
# Logic shifters : 1
|
|
64-bit shifter logical right : 1
|
|
# FSMs : 18
|
|
# Xors : 93
|
|
1-bit xor2 : 67
|
|
32-bit xor2 : 26
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
WARNING:Xst:1989 - Unit <lm32_2nd>: instances <u20>, <u21> of unit <DummySlave> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <lm32_2nd>: instances <u20>, <u22> of unit <DummySlave> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <lm32_2nd>: instances <u20>, <u23> of unit <DummySlave> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <lm32_2nd>: instances <u20>, <u24> of unit <DummySlave> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <lm32_2nd>: instances <u20>, <u25> of unit <DummySlave> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[1].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[2].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[3].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[4].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[5].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1989 - Unit <wb_gpio_port>: instances <GEN_SYNC_FFS[0].INPUT_SYNC>, <GEN_SYNC_FFS[6].INPUT_SYNC> of unit <gc_sync_ffs> are equivalent, second instance is removed
|
|
WARNING:Xst:1710 - FF/Latch <rx_rcv_init> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_debounceer.deb_buf_0> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_deb> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_0> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_6> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_start_detect.rx_data_old> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_1> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_debounceer.deb_buf_1> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_2> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_debounceer.deb_buf_2> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_5> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_debounceer.deb_buf_3> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_3> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_4> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_4> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_3> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_5> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_2> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_tmp_6> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_1> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_data_0> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30>
|
|
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31>
|
|
INFO:Xst:2261 - The FF/Latch <i_cyc_o> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_stb_o>
|
|
INFO:Xst:2261 - The FF/Latch <d_stb_o> in Unit <lm32_load_store_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <d_cyc_o>
|
|
WARNING:Xst:1710 - FF/Latch <matrix_old_2_0> (without init value) has a constant value of 0 in block <xwb_crossbar_1>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <matrix_old_2_1> (without init value) has a constant value of 0 in block <xwb_crossbar_1>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <matrix_old_2_2> (without init value) has a constant value of 0 in block <xwb_crossbar_1>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <npulse_o> (without init value) has a constant value of 0 in block <gc_sync_ffs>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ppulse_o> (without init value) has a constant value of 0 in block <gc_sync_ffs>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync0> (without init value) has a constant value of 0 in block <gc_sync_ffs>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync1> (without init value) has a constant value of 0 in block <gc_sync_ffs>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sync2> (without init value) has a constant value of 0 in block <gc_sync_ffs>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <u7/u0/O_n> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u8/u1/O_n> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u8/u0/O_n> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u6/u1/O_n> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u6/u0/O_n> of sequential type is unconnected in block <fpga>.
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/FSM_1> on signal <state[1:4]> with sequential encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
0000 | 0000
|
|
0001 | 0001
|
|
0110 | 0010
|
|
0101 | 0011
|
|
0010 | 0100
|
|
0011 | 0101
|
|
0100 | 0110
|
|
0111 | 0111
|
|
1000 | 1000
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/FSM_0> on signal <state[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
0001 | 00
|
|
0010 | 01
|
|
0100 | 11
|
|
1000 | 10
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/FSM_2> on signal <state[1:3]> with user encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
000 | 000
|
|
001 | 001
|
|
010 | 010
|
|
011 | 011
|
|
100 | 100
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/FSM_7> on signal <state_ts[1:1]> with sequential encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 0
|
|
01 | 1
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/FSM_8> on signal <n_state[1:2]> with user encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
10 | 10
|
|
11 | 11
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/FSM_9> on signal <state_down[1:3]> with user encoding.
|
|
-------------------------
|
|
State | Encoding
|
|
-------------------------
|
|
header | 000
|
|
idle | 001
|
|
down_header | 010
|
|
down_data | 011
|
|
waiting | 100
|
|
-------------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/FSM_11> on signal <rx_fsm[1:2]> with sequential encoding.
|
|
--------------------
|
|
State | Encoding
|
|
--------------------
|
|
idle | 00
|
|
data | 01
|
|
parity | 10
|
|
stop1 | unreached
|
|
stop2 | unreached
|
|
--------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/FSM_10> on signal <tx_fsm[1:3]> with user encoding.
|
|
--------------------
|
|
State | Encoding
|
|
--------------------
|
|
idle | 000
|
|
data | 001
|
|
parity | 010
|
|
stop1 | 011
|
|
stop2 | 100
|
|
--------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[2].channel_tdc/c_dru/FSM_12> on signal <p_state[1:2]> with user encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_dru/FSM_12> on signal <p_state[1:2]> with user encoding.
|
|
Optimizing FSM <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_dru/FSM_12> on signal <p_state[1:2]> with user encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
11 | 11
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u12/U_Wrapped_UART/gen_phys_uart.U_TX/FSM_3> on signal <state[1:4]> with user encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
0000 | 0000
|
|
0001 | 0001
|
|
0100 | 0100
|
|
0011 | 0011
|
|
1000 | 1000
|
|
1001 | 1001
|
|
1010 | 1010
|
|
1011 | 1011
|
|
1100 | 1100
|
|
1101 | 1101
|
|
1110 | 1110
|
|
1111 | 1111
|
|
0010 | 0010
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/FSM_4> on signal <state[1:4]> with sequential encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
0000 | 0000
|
|
1000 | 0001
|
|
1001 | 0010
|
|
1010 | 0011
|
|
1011 | 0100
|
|
1100 | 0101
|
|
1101 | 0110
|
|
1110 | 0111
|
|
1111 | 1000
|
|
0001 | 1001
|
|
-------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/FSM_5> on signal <c_state[1:3]> with user encoding.
|
|
Optimizing FSM <u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/FSM_5> on signal <c_state[1:3]> with user encoding.
|
|
----------------------
|
|
State | Encoding
|
|
----------------------
|
|
st_idle | 000
|
|
st_start | 001
|
|
st_read | 010
|
|
st_write | 011
|
|
st_ack | 100
|
|
st_stop | 101
|
|
----------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u7/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/FSM_6> on signal <c_state[1:5]> with user encoding.
|
|
Optimizing FSM <u0/u14/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/FSM_6> on signal <c_state[1:5]> with user encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
idle | 00000
|
|
start_a | 00001
|
|
start_b | 00010
|
|
start_c | 00011
|
|
start_d | 00100
|
|
start_e | 00101
|
|
stop_a | 00110
|
|
stop_b | 00111
|
|
stop_c | 01000
|
|
stop_d | 01001
|
|
rd_a | 01010
|
|
rd_b | 01011
|
|
rd_c | 01100
|
|
rd_d | 01101
|
|
wr_a | 01110
|
|
wr_b | 01111
|
|
wr_c | 10000
|
|
wr_d | 10001
|
|
---------------------
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
Optimizing FSM <u0/u13/U_multiboot/Wrapped_multiboot/UU_Multiboot/FSM_13> on signal <NEXT_STATE[1:12]> with one-hot encoding.
|
|
--------------------------
|
|
State | Encoding
|
|
--------------------------
|
|
state_00 | 000000000001
|
|
state_01 | 000000000010
|
|
state_02 | 000000000100
|
|
state_03 | 000000001000
|
|
state_04 | 000000010000
|
|
state_05 | 000000100000
|
|
state_06 | 000001000000
|
|
state_07 | 000010000000
|
|
state_08 | 000100000000
|
|
state_09 | 001000000000
|
|
state_10 | 010000000000
|
|
state_11 | 100000000000
|
|
--------------------------
|
|
WARNING:Xst:1710 - FF/Latch <i_cti_o_1> (without init value) has a constant value of 1 in block <lm32_instruction_unit_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <i_index_0> has a constant value of 1 in block <mux_tdc>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_index_1> has a constant value of 1 in block <mux_tdc>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_index_2> has a constant value of 1 in block <mux_tdc>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <i_index_3> has a constant value of 1 in block <mux_tdc>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <index_ch_3> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_4> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_5> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_6> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_7> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_8> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_9> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_10> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_11> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_12> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_13> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_14> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_15> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_16> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_17> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_18> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_19> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_20> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_21> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_22> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_23> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_24> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_25> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_26> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_27> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_28> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_29> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:2677 - Node <index_ch_30> of sequential type is unconnected in block <mux_tdc>.
|
|
WARNING:Xst:1710 - FF/Latch <rx_par_bit> (without init value) has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1293 - FF/Latch <count_ts_0> has a constant value of 0 in block <DRU>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <count_ts_1> has a constant value of 0 in block <DRU>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <count_8> of sequential type is unconnected in block <DRU>.
|
|
WARNING:Xst:1710 - FF/Latch <inst_LPM_FF1_4> (without init value) has a constant value of 0 in block <generic_dpram_sameclock>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_3> (without init value) has a constant value of 0 in block <generic_dpram_sameclock>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_2> (without init value) has a constant value of 0 in block <generic_dpram_sameclock>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_1> (without init value) has a constant value of 0 in block <generic_dpram_sameclock>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_0> (without init value) has a constant value of 0 in block <generic_dpram_sameclock>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <matrix_old_2_3> (without init value) has a constant value of 0 in block <xwb_crossbar_1>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <out_reg_7> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_8> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_9> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_10> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_11> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_12> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_13> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_14> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_15> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <wb_gpio_port>.
|
|
WARNING:Xst:2677 - Node <u3/Count_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u3/Count_31> of sequential type is unconnected in block <fpga>.
|
|
INFO:Xst:2261 - The FF/Latch <i_cti_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_cti_o_2>
|
|
INFO:Xst:2261 - The FF/Latch <I_2> in Unit <multiboot> is equivalent to the following 5 FFs/Latches, which will be removed : <I_16> <I_20> <I_24> <I_28> <I_30>
|
|
INFO:Xst:2261 - The FF/Latch <I_0> in Unit <multiboot> is equivalent to the following 6 FFs/Latches, which will be removed : <I_3> <I_12> <I_21> <I_25> <I_29> <I_31>
|
|
INFO:Xst:2261 - The FF/Latch <I_1> in Unit <multiboot> is equivalent to the following 6 FFs/Latches, which will be removed : <I_9> <I_11> <I_13> <I_15> <I_19> <I_23>
|
|
INFO:Xst:2261 - The FF/Latch <NEXT_STATE_FSM_FFd8> in Unit <multiboot> is equivalent to the following 3 FFs/Latches, which will be removed : <I_10> <I_14> <I_18>
|
|
WARNING:Xst:2042 - Unit wb_gpio_port: 7 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>.
|
|
|
|
Optimizing unit <fpga> ...
|
|
|
|
Optimizing unit <xwb_lm32> ...
|
|
|
|
Optimizing unit <lm32_cpu_medium_icache_debug> ...
|
|
|
|
Optimizing unit <lm32_interrupt_medium_icache_debug> ...
|
|
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_4> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_3> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_2> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_4> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_3> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_2> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
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Optimizing unit <lm32_jtag_medium_icache_debug> ...
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Optimizing unit <lm32_instruction_unit_medium_icache_debug> ...
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Optimizing unit <lm32_icache_medium_icache_debug> ...
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Optimizing unit <lm32_ram_2> ...
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Optimizing unit <lm32_load_store_unit_medium_icache_debug> ...
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Optimizing unit <lm32_shifter> ...
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Optimizing unit <lm32_multiplier> ...
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Optimizing unit <lm32_debug_medium_icache_debug> ...
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Optimizing unit <lm32_decoder_medium_icache_debug> ...
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Optimizing unit <jtag_cores> ...
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Optimizing unit <wb_slave_adapter_3> ...
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Optimizing unit <tdc_master_top> ...
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Optimizing unit <mux_tdc> ...
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Optimizing unit <uart> ...
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Optimizing unit <tdc_top> ...
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Optimizing unit <DRU> ...
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Optimizing unit <xwb_dpram> ...
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Optimizing unit <generic_dpram_sameclock> ...
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Optimizing unit <xwb_crossbar_1> ...
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Optimizing unit <sdb_rom_1> ...
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Optimizing unit <xwb_crossbar_2> ...
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Optimizing unit <wb_simple_uart> ...
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Optimizing unit <simple_uart_wb> ...
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WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
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Optimizing unit <uart_baud_gen> ...
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Optimizing unit <uart_async_tx> ...
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Optimizing unit <uart_async_rx> ...
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Optimizing unit <wb_tics> ...
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Optimizing unit <wb_gpio_port> ...
|
|
|
|
Optimizing unit <i2c_master_top> ...
|
|
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|
Optimizing unit <i2c_master_byte_ctrl> ...
|
|
|
|
Optimizing unit <i2c_master_bit_ctrl> ...
|
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Optimizing unit <wb_slave_adapter_5> ...
|
|
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Optimizing unit <spi_top> ...
|
|
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Optimizing unit <spi_shift> ...
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Optimizing unit <spi_clgen> ...
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Optimizing unit <multiboot_master_top> ...
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Optimizing unit <multiboot> ...
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WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_31> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_24> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_23> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_22> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_21> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_20> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_19> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_18> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/data_addr_reg_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_31> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_24> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_23> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_22> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_21> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_20> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_19> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_18> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/inst_addr_reg_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_31> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_24> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_23> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_22> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_21> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_20> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_19> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_18> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_24> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_23> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_22> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_21> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_20> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_19> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_18> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_17> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_16> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_15> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_14> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_13> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_12> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_11> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_10> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_9> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_8> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_7> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_6> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_5> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_4> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_3> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_2> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_31> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_30> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_29> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_28> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_27> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_26> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_25> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_24> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_23> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_22> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_21> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_20> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_19> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_18> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/d_adr_o_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_7> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_6> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_5> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_4> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_3> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_2> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/tx_data_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_15> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_14> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_13> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_12> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_11> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_10> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_9> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_8> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_7> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_6> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_5> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_4> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_3> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_2> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/word_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_8> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_7> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_6> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_5> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_4> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_3> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_2> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_gen.counter_0> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_data_cnt_2> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_data_cnt_1> of sequential type is unconnected in block <fpga>.
|
|
WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_data_cnt_0> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_fsm_FSM_FFd2> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_fsm_FSM_FFd1> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_ready> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_par_bit> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_7> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_6> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_5> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_4> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_3> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_2> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_1> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/tx_data_tmp_0> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/u/rx_clk_en> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u4/slave2_out_ack> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u12/U_Wrapped_UART/U_WB_SLAVE/host_rack_o> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u12/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_error> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_6> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_5> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_4> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_3> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_2> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_1> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u5/Wrapped_GPIO/out_reg_0> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u14/U_Wrapped_I2C/Wrapped_I2C/wb_inta_o> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u7/U_Wrapped_I2C/Wrapped_I2C/wb_inta_o> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:2677 - Node <u0/u18/U_Wrapped_SPI/Wrapped_SPI/wb_int_o> of sequential type is unconnected in block <fpga>.
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WARNING:Xst:638 - in unit fpga Conflict on KEEP property on signal u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost.
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WARNING:Xst:638 - in unit fpga Conflict on KEEP property on signal u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost.
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WARNING:Xst:638 - in unit fpga Conflict on KEEP property on signal u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> u0/u4/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_6> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_7> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_8> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_9> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_10> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_11> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_12> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_13> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_14> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_15> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_16> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_17> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_18> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_19> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_20> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_21> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_22> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_23> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_24> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_25> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_26> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_27> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_28> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_29> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_30> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1293 - FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/i_index_31> has a constant value of 0 in block <fpga>. This FF/Latch will be trimmed during the optimization process.
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INFO:Xst:2261 - The FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_27> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/duration_26>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_0> in Unit <fpga> is equivalent to the following 2 FFs/Latches, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_0> <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_0>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_1> in Unit <fpga> is equivalent to the following 2 FFs/Latches, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_1> <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_1>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_2> in Unit <fpga> is equivalent to the following 2 FFs/Latches, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_2> <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/sign_extend_x>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_x> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_x>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_0>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_1>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_2>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_3>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_4>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_5>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_6>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_7>
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INFO:Xst:2261 - The FF/Latch <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_4> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/n_time_slice_30>
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INFO:Xst:2261 - The FF/Latch <u0/u12/U_Wrapped_UART/U_WB_SLAVE/ack_sreg> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u12/U_Wrapped_UART/U_WB_SLAVE/ack_in_progress>
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INFO:Xst:2261 - The FF/Latch <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_3> in Unit <fpga> is equivalent to the following FF/Latch, which will be removed : <u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/direction_x>
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 3.
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