You've already forked gitified_old_clb_svn
1268 lines
104 KiB
Plaintext
1268 lines
104 KiB
Plaintext
--------------------------------------------------------------------------------
|
|
Release 14.2 Trace (nt)
|
|
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
|
|
|
C:\Xilinx\14.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
|
|
3 -fastpaths -xml fpga.twx fpga.ncd -o fpga.twr fpga.pcf
|
|
|
|
Design file: fpga.ncd
|
|
Physical constraint file: fpga.pcf
|
|
Device,package,speed: xc7k325t,ffg900,C,-2 (PRELIMINARY 1.06 2012-07-14)
|
|
Report level: verbose report
|
|
|
|
Environment Variable Effect
|
|
-------------------- ------
|
|
NONE No environment variables were set
|
|
--------------------------------------------------------------------------------
|
|
|
|
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
|
option. All paths that are not constrained will be reported in the
|
|
unconstrained paths section(s) of the report.
|
|
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
|
a 50 Ohm transmission line loading model. For the details of this model,
|
|
and for more information on accounting for different loading conditions,
|
|
please see the device datasheet.
|
|
|
|
================================================================================
|
|
Timing constraint: TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 component switching limit errors)
|
|
Minimum period is 4.000ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Component Switching Limit Checks: TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
Slack: 4.000ns (period - (min low pulse limit / (low pulse / period)))
|
|
Period: 8.000ns
|
|
Low pulse: 4.000ns
|
|
Low pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
|
|
Physical resource: u1/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u1/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X0Y1.CLKIN1
|
|
Clock network: u1/clkin1
|
|
--------------------------------------------------------------------------------
|
|
Slack: 4.000ns (period - (min high pulse limit / (high pulse / period)))
|
|
Period: 8.000ns
|
|
High pulse: 4.000ns
|
|
High pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
|
|
Physical resource: u1/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u1/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X0Y1.CLKIN1
|
|
Clock network: u1/clkin1
|
|
--------------------------------------------------------------------------------
|
|
Slack: 6.592ns (period - min period limit)
|
|
Period: 8.000ns
|
|
Min period limit: 1.408ns (710.227MHz) (Tibiper)
|
|
Physical resource: u5/I
|
|
Logical resource: u5/I
|
|
Location pin: IBUFDS_GTE2_X0Y4.I
|
|
Clock network: ClkI_p_IBUF
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5
|
|
HIGH 50%;
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1696795 paths analyzed, 13209 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
|
|
Minimum period is 12.252ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (SLICE_X36Y183.C5), 22 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 0.937ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 2.635ns (Levels of Logic = 2)
|
|
Clock Path Skew: -0.229ns (1.149 - 1.378)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 12.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.199ns
|
|
|
|
Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.129ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X54Y127.BQ Tcko 0.259 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<7>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9
|
|
SLICE_X36Y183.B6 net (fanout=1) 2.069 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<7>
|
|
SLICE_X36Y183.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911
|
|
SLICE_X36Y183.C5 net (fanout=1) 0.255 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291
|
|
SLICE_X36Y183.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
------------------------------------------------- ---------------------------
|
|
Total 2.635ns (0.311ns logic, 2.324ns route)
|
|
(11.8% logic, 88.2% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 11.976ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u0/inst_was_busy (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (FF)
|
|
Requirement: 16.000ns
|
|
Data Path Delay: 3.654ns (Levels of Logic = 4)
|
|
Clock Path Skew: -0.294ns (1.044 - 1.338)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.076ns
|
|
|
|
Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.135ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u0/inst_was_busy to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X42Y148.AQ Tcko 0.259 u0/u0/inst_was_busy
|
|
u0/u0/inst_was_busy
|
|
SLICE_X22Y158.C1 net (fanout=44) 1.194 u0/u0/inst_was_busy
|
|
SLICE_X22Y158.CMUX Tilo 0.135 u0/cbar_slave_i[1]_adr<4>
|
|
u0/u0/mux5711
|
|
SLICE_X23Y177.A1 net (fanout=9) 0.919 u0/cbar_slave_i[1]_adr<3>
|
|
SLICE_X23Y177.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/_n0073_inv
|
|
u0/u9/crossbar/master_oe[1]_adr<3>1
|
|
SLICE_X36Y183.B2 net (fanout=34) 0.797 u0/secbar_master_o[1]_adr<3>
|
|
SLICE_X36Y183.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911
|
|
SLICE_X36Y183.C5 net (fanout=1) 0.255 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291
|
|
SLICE_X36Y183.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
------------------------------------------------- ---------------------------
|
|
Total 3.654ns (0.489ns logic, 3.165ns route)
|
|
(13.4% logic, 86.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 12.109ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u0/inst_addr_reg_3 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (FF)
|
|
Requirement: 16.000ns
|
|
Data Path Delay: 3.519ns (Levels of Logic = 4)
|
|
Clock Path Skew: -0.296ns (1.044 - 1.340)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.076ns
|
|
|
|
Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.135ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u0/inst_addr_reg_3 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X39Y145.BQ Tcko 0.223 u0/u0/inst_addr_reg<5>
|
|
u0/u0/inst_addr_reg_3
|
|
SLICE_X22Y158.C3 net (fanout=3) 1.091 u0/u0/inst_addr_reg<3>
|
|
SLICE_X22Y158.CMUX Tilo 0.139 u0/cbar_slave_i[1]_adr<4>
|
|
u0/u0/mux5711
|
|
SLICE_X23Y177.A1 net (fanout=9) 0.919 u0/cbar_slave_i[1]_adr<3>
|
|
SLICE_X23Y177.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/_n0073_inv
|
|
u0/u9/crossbar/master_oe[1]_adr<3>1
|
|
SLICE_X36Y183.B2 net (fanout=34) 0.797 u0/secbar_master_o[1]_adr<3>
|
|
SLICE_X36Y183.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911
|
|
SLICE_X36Y183.C5 net (fanout=1) 0.255 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291
|
|
SLICE_X36Y183.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
------------------------------------------------- ---------------------------
|
|
Total 3.519ns (0.457ns logic, 3.062ns route)
|
|
(13.0% logic, 87.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (SLICE_X36Y183.C3), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 1.050ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 2.518ns (Levels of Logic = 1)
|
|
Clock Path Skew: -0.233ns (1.149 - 1.382)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 12.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.199ns
|
|
|
|
Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.129ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X50Y119.BQ Tcko 0.259 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc4<7>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9
|
|
SLICE_X36Y183.C3 net (fanout=1) 2.250 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc4<7>
|
|
SLICE_X36Y183.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7
|
|
------------------------------------------------- ---------------------------
|
|
Total 2.518ns (0.268ns logic, 2.250ns route)
|
|
(10.6% logic, 89.4% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4 (SLICE_X37Y180.D5), 22 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 1.350ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 2.222ns (Levels of Logic = 2)
|
|
Clock Path Skew: -0.229ns (1.147 - 1.376)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 12.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.199ns
|
|
|
|
Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.129ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X54Y126.CQ Tcko 0.259 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6
|
|
SLICE_X37Y180.B5 net (fanout=1) 1.685 u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<4>
|
|
SLICE_X37Y180.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611
|
|
SLICE_X37Y180.D5 net (fanout=1) 0.243 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261
|
|
SLICE_X37Y180.CLK Tas -0.008 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 2.222ns (0.294ns logic, 1.928ns route)
|
|
(13.2% logic, 86.8% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 12.048ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4 (FF)
|
|
Requirement: 16.000ns
|
|
Data Path Delay: 3.579ns (Levels of Logic = 4)
|
|
Clock Path Skew: -0.297ns (1.042 - 1.339)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.076ns
|
|
|
|
Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.135ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X39Y142.CQ Tcko 0.223 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o<2>
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2
|
|
SLICE_X23Y156.C2 net (fanout=8) 1.141 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o<2>
|
|
SLICE_X23Y156.CMUX Tilo 0.139 u0/cbar_slave_i[1]_adr<5>
|
|
u0/u0/mux5411
|
|
SLICE_X40Y176.B5 net (fanout=42) 0.994 u0/cbar_slave_i[1]_adr<2>
|
|
SLICE_X40Y176.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<19>
|
|
u0/u9/crossbar/master_oe[1]_adr<2>1
|
|
SLICE_X37Y180.B2 net (fanout=33) 0.761 u0/secbar_master_o[1]_adr<2>
|
|
SLICE_X37Y180.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611
|
|
SLICE_X37Y180.D5 net (fanout=1) 0.243 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261
|
|
SLICE_X37Y180.CLK Tas -0.008 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 3.579ns (0.440ns logic, 3.139ns route)
|
|
(12.3% logic, 87.7% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 12.064ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u0/inst_was_busy (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4 (FF)
|
|
Requirement: 16.000ns
|
|
Data Path Delay: 3.564ns (Levels of Logic = 4)
|
|
Clock Path Skew: -0.296ns (1.042 - 1.338)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.076ns
|
|
|
|
Clock Uncertainty: 0.076ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.135ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u0/inst_was_busy to u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X42Y148.AQ Tcko 0.259 u0/u0/inst_was_busy
|
|
u0/u0/inst_was_busy
|
|
SLICE_X23Y156.C1 net (fanout=44) 1.090 u0/u0/inst_was_busy
|
|
SLICE_X23Y156.CMUX Tilo 0.139 u0/cbar_slave_i[1]_adr<5>
|
|
u0/u0/mux5411
|
|
SLICE_X40Y176.B5 net (fanout=42) 0.994 u0/cbar_slave_i[1]_adr<2>
|
|
SLICE_X40Y176.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<19>
|
|
u0/u9/crossbar/master_oe[1]_adr<2>1
|
|
SLICE_X37Y180.B2 net (fanout=33) 0.761 u0/secbar_master_o[1]_adr<2>
|
|
SLICE_X37Y180.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611
|
|
SLICE_X37Y180.D5 net (fanout=1) 0.243 u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261
|
|
SLICE_X37Y180.CLK Tas -0.008 u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 3.564ns (0.476ns logic, 3.088ns route)
|
|
(13.4% logic, 86.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30 (SLICE_X20Y99.A4), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.040ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4 (FF)
|
|
Destination: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.306ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.266ns (0.795 - 0.529)
|
|
Source Clock: clk_62_5_o rising at 16.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4 to u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X23Y106.BQ Tcko 0.100 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<5>
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4
|
|
SLICE_X20Y99.A4 net (fanout=38) 0.265 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<4>
|
|
SLICE_X20Y99.CLK Tah (-Th) 0.059 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result<31>
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/Sh1581
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.306ns (0.041ns logic, 0.265ns route)
|
|
(13.4% logic, 86.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31 (SLICE_X20Y99.B4), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.040ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4 (FF)
|
|
Destination: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.306ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.266ns (0.795 - 0.529)
|
|
Source Clock: clk_62_5_o rising at 16.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4 to u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X23Y106.BQ Tcko 0.100 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<5>
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4
|
|
SLICE_X20Y99.B4 net (fanout=38) 0.265 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<4>
|
|
SLICE_X20Y99.CLK Tah (-Th) 0.059 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result<31>
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/Sh1591
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.306ns (0.041ns logic, 0.265ns route)
|
|
(13.4% logic, 86.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11 (SLICE_X18Y149.D6), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.048ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u1/crossbar/matrix_old_0_0 (FF)
|
|
Destination: u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.315ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.267ns (0.796 - 0.529)
|
|
Source Clock: clk_62_5_o rising at 16.000ns
|
|
Destination Clock: clk_62_5_o rising at 16.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u1/crossbar/matrix_old_0_0 to u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X23Y154.BQ Tcko 0.100 u0/u1/crossbar/matrix_old_0<3>
|
|
u0/u1/crossbar/matrix_old_0_0
|
|
SLICE_X18Y149.D6 net (fanout=76) 0.274 u0/u1/crossbar/matrix_old_0<0>
|
|
SLICE_X18Y149.CLK Tah (-Th) 0.059 u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m<11>
|
|
u0/u1/crossbar/slave_o[0]_dat<11>1
|
|
u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.315ns (0.041ns logic, 0.274ns route)
|
|
(13.0% logic, 87.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Component Switching Limit Checks: TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.929ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.071ns (933.707MHz) (Tmmcmper_CLKOUT(Foutmax))
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKOUT0
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKOUT0
|
|
Location pin: MMCME2_ADV_X1Y2.CLKOUT0
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout0
|
|
--------------------------------------------------------------------------------
|
|
Slack: 10.000ns (period - (min low pulse limit / (low pulse / period)))
|
|
Period: 16.000ns
|
|
Low pulse: 8.000ns
|
|
Low pulse limit: 3.000ns (Tmmcmpw_CLKIN1_50_100)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X1Y2.CLKIN1
|
|
Clock network: clk_62_5_o
|
|
--------------------------------------------------------------------------------
|
|
Slack: 10.000ns (period - (min high pulse limit / (high pulse / period)))
|
|
Period: 16.000ns
|
|
High pulse: 8.000ns
|
|
High pulse limit: 3.000ns (Tmmcmpw_CLKIN1_50_100)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X1Y2.CLKIN1
|
|
Clock network: clk_62_5_o
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0
|
|
= PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0"
|
|
TS_u1_clkout0 / 4 HIGH 50%;
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 component switching limit errors)
|
|
Minimum period is 2.334ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0"
|
|
TS_u1_clkout0 / 4 HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
Slack: 1.666ns (period - (min low pulse limit / (low pulse / period)))
|
|
Period: 4.000ns
|
|
Low pulse: 2.000ns
|
|
Low pulse limit: 1.167ns (Tmmcmpw_CLKIN1_250_300)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X0Y0.CLKIN1
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk0_in
|
|
--------------------------------------------------------------------------------
|
|
Slack: 1.666ns (period - (min high pulse limit / (high pulse / period)))
|
|
Period: 4.000ns
|
|
High pulse: 2.000ns
|
|
High pulse limit: 1.167ns (Tmmcmpw_CLKIN1_250_300)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1
|
|
Location pin: MMCME2_ADV_X0Y0.CLKIN1
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk0_in
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.592ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.408ns (710.227MHz) (Tbcper_I(Fmax))
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf/I0
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf/I0
|
|
Location pin: BUFGCTRL_X0Y3.I0
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout0
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 =
|
|
PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1 ns
|
|
HIGH 50%;
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 component switching limit errors)
|
|
Minimum period is 1.408ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1
|
|
ns HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.592ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.408ns (710.227MHz) (Tbcper_I(Fmax))
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf/I0
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf/I0
|
|
Location pin: BUFGCTRL_X0Y2.I0
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout1
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 =
|
|
PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
77861 paths analyzed, 4367 endpoints analyzed, 131 failing endpoints
|
|
131 timing errors detected. (131 setup errors, 0 hold errors, 0 component switching limit errors)
|
|
Minimum period is 5.473ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19 (SLICE_X9Y122.D6), 185 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.473ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.392ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.D6 net (fanout=33) 0.496 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.392ns (2.225ns logic, 3.167ns route)
|
|
(41.3% logic, 58.7% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.473ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.392ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.D6 net (fanout=33) 0.496 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.392ns (2.225ns logic, 3.167ns route)
|
|
(41.3% logic, 58.7% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.395ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.314ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO20 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C2 net (fanout=1) 0.712 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.D6 net (fanout=33) 0.496 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.314ns (2.225ns logic, 3.089ns route)
|
|
(41.9% logic, 58.1% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29 (SLICE_X9Y122.C6), 185 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.451ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.370ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.C6 net (fanout=33) 0.474 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.370ns (2.225ns logic, 3.145ns route)
|
|
(41.4% logic, 58.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.451ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.370ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.C6 net (fanout=33) 0.474 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.370ns (2.225ns logic, 3.145ns route)
|
|
(41.4% logic, 58.6% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.373ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.292ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.012ns (0.609 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO20 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C2 net (fanout=1) 0.712 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.C6 net (fanout=33) 0.474 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y122.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.292ns (2.225ns logic, 3.067ns route)
|
|
(42.0% logic, 58.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4 (SLICE_X9Y119.A6), 185 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.379ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.302ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.008ns (0.613 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.A6 net (fanout=33) 0.406 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.302ns (2.225ns logic, 3.077ns route)
|
|
(42.0% logic, 58.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.379ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.302ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.008ns (0.613 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO16 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C1 net (fanout=1) 0.790 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.A6 net (fanout=33) 0.406 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.302ns (2.225ns logic, 3.077ns route)
|
|
(42.0% logic, 58.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): -1.301ns (requirement - (data path - clock path skew + uncertainty))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram (RAM)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4 (FF)
|
|
Requirement: 4.000ns
|
|
Data Path Delay: 5.224ns (Levels of Logic = 6)
|
|
Clock Path Skew: -0.008ns (0.613 - 0.621)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.069ns
|
|
|
|
Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Maximum Data Path at Slow Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
RAMB36_X2Y21.DOBDO20 Trcko_DOB 1.800 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram
|
|
SLICE_X51Y110.C2 net (fanout=1) 0.712 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33>
|
|
SLICE_X51Y110.CMUX Tilo 0.244 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D1 net (fanout=1) 0.629 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21
|
|
SLICE_X49Y113.D Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C5 net (fanout=1) 0.150 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
SLICE_X49Y113.C Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0
|
|
SLICE_X15Y117.B6 net (fanout=1) 0.791 N488
|
|
SLICE_X15Y117.B Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24
|
|
SLICE_X12Y119.A6 net (fanout=5) 0.311 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o
|
|
SLICE_X12Y119.A Tilo 0.043 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.A6 net (fanout=33) 0.406 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot
|
|
SLICE_X9Y119.CLK Tas 0.009 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4
|
|
------------------------------------------------- ---------------------------
|
|
Total 5.224ns (2.225ns logic, 2.999ns route)
|
|
(42.6% logic, 57.4% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6 (SLICE_X60Y98.CX), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.008ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.271ns (Levels of Logic = 0)
|
|
Clock Path Skew: 0.263ns (0.747 - 0.484)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X56Y102.CQ Tcko 0.118 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<1><7>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6
|
|
SLICE_X60Y98.CX net (fanout=1) 0.200 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<1><6>
|
|
SLICE_X60Y98.CLK Tckdi (-Th) 0.047 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<2><9>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.271ns (0.071ns logic, 0.200ns route)
|
|
(26.2% logic, 73.8% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0 (SLICE_X18Y116.CE), 7 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.030ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u7/u1/O_n (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.478ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.186ns (0.856 - 0.670)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Clock Uncertainty: 0.262ns
|
|
|
|
Clock Uncertainty: 0.262ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.254ns
|
|
Phase Error (PE): 0.129ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u7/u1/O_n to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X7Y115.AQ Tcko 0.100 u7/u1/O_n
|
|
u7/u1/O_n
|
|
SLICE_X18Y116.C5 net (fanout=245) 0.326 u7/u1/O_n
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.478ns (0.098ns logic, 0.380ns route)
|
|
(20.5% logic, 79.5% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.323ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.354ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.031ns (0.363 - 0.332)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X11Y117.BQ Tcko 0.100 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2
|
|
SLICE_X18Y116.C6 net (fanout=41) 0.202 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.354ns (0.098ns logic, 0.256ns route)
|
|
(27.7% logic, 72.3% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.473ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.504ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.031ns (0.363 - 0.332)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X12Y117.CQ Tcko 0.118 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
SLICE_X18Y116.C3 net (fanout=46) 0.334 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.504ns (0.116ns logic, 0.388ns route)
|
|
(23.0% logic, 77.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1 (SLICE_X18Y116.CE), 7 paths
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.030ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u7/u1/O_n (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.478ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.186ns (0.856 - 0.670)
|
|
Source Clock: clk_62_5_o rising at 0.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 0.000ns
|
|
Clock Uncertainty: 0.262ns
|
|
|
|
Clock Uncertainty: 0.262ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.070ns
|
|
Discrete Jitter (DJ): 0.254ns
|
|
Phase Error (PE): 0.129ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u7/u1/O_n to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X7Y115.AQ Tcko 0.100 u7/u1/O_n
|
|
u7/u1/O_n
|
|
SLICE_X18Y116.C5 net (fanout=245) 0.326 u7/u1/O_n
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.478ns (0.098ns logic, 0.380ns route)
|
|
(20.5% logic, 79.5% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.323ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.354ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.031ns (0.363 - 0.332)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X11Y117.BQ Tcko 0.100 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2
|
|
SLICE_X18Y116.C6 net (fanout=41) 0.202 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.354ns (0.098ns logic, 0.256ns route)
|
|
(27.7% logic, 72.3% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 0.473ns (requirement - (clock path skew + uncertainty - data path))
|
|
Source: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1 (FF)
|
|
Destination: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1 (FF)
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 0.504ns (Levels of Logic = 1)
|
|
Clock Path Skew: 0.031ns (0.363 - 0.332)
|
|
Source Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Destination Clock: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0 rising at 4.000ns
|
|
Clock Uncertainty: 0.000ns
|
|
|
|
Minimum Data Path at Fast Process Corner: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1 to u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
SLICE_X12Y117.CQ Tcko 0.118 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
SLICE_X18Y116.C3 net (fanout=46) 0.334 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1
|
|
SLICE_X18Y116.C Tilo 0.028 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1
|
|
SLICE_X18Y116.CE net (fanout=1) 0.054 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv
|
|
SLICE_X18Y116.CLK Tckce (-Th) 0.030 u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1>
|
|
u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1
|
|
------------------------------------------------- ---------------------------
|
|
Total 0.504ns (0.116ns logic, 0.388ns route)
|
|
(23.0% logic, 77.0% route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP
|
|
"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
|
|
TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.161ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.839ns (543.774MHz) (Trper_CLKA)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK
|
|
Location pin: RAMB18_X2Y47.CLKARDCLK
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.161ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.839ns (543.774MHz) (Trper_CLKA)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKBWRCLK
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKBWRCLK
|
|
Location pin: RAMB18_X2Y47.CLKBWRCLK
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0
|
|
--------------------------------------------------------------------------------
|
|
Slack: 2.161ns (period - min period limit)
|
|
Period: 4.000ns
|
|
Min period limit: 1.839ns (543.774MHz) (Trper_CLKA)
|
|
Physical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK
|
|
Logical resource: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK
|
|
Location pin: RAMB18_X2Y46.RDCLK
|
|
Clock network: u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Derived Constraint Report
|
|
Derived Constraints for TS_ClkI_p
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
|
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|TS_ClkI_p | 8.000ns| 4.000ns| 10.946ns| 0| 131| 0| 1774656|
|
|
| TS_u1_clkout0 | 16.000ns| 12.252ns| 21.892ns| 0| 131| 1696795| 77861|
|
|
| TS_u0_u11_U_Wrapped_tdc_Wrapp| 4.000ns| 2.334ns| 5.473ns| 0| 131| 0| 77861|
|
|
| ed_tdc_U_Mux_tdc_dcm250_clkou| | | | | | | |
|
|
| t0 | | | | | | | |
|
|
| TS_u0_u11_U_Wrapped_tdc_Wrap| 4.000ns| 1.408ns| N/A| 0| 0| 0| 0|
|
|
| ped_tdc_U_Mux_tdc_dcm2_clkou| | | | | | | |
|
|
| t1 | | | | | | | |
|
|
| TS_u0_u11_U_Wrapped_tdc_Wrap| 4.000ns| 5.473ns| N/A| 131| 0| 77861| 0|
|
|
| ped_tdc_U_Mux_tdc_dcm2_clkou| | | | | | | |
|
|
| t0 | | | | | | | |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|
|
1 constraint not met.
|
|
|
|
|
|
Data Sheet report:
|
|
-----------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
Clock to Setup on destination clock ClkI_n
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
ClkI_n | 8.433| | | |
|
|
ClkI_p | 8.433| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
Clock to Setup on destination clock ClkI_p
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
ClkI_n | 8.433| | | |
|
|
ClkI_p | 8.433| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
|
|
Timing summary:
|
|
---------------
|
|
|
|
Timing errors: 131 Score: 65286 (Setup/Max: 65286, Hold: 0)
|
|
|
|
Constraints cover 1774656 paths, 0 nets, and 26189 connections
|
|
|
|
Design statistics:
|
|
Minimum period: 12.252ns{1} (Maximum frequency: 81.619MHz)
|
|
|
|
|
|
------------------------------------Footnotes-----------------------------------
|
|
1) The minimum period statistic assumes all single cycle delays.
|
|
|
|
Analysis completed Fri Jul 19 19:16:58 2013
|
|
--------------------------------------------------------------------------------
|
|
|
|
Trace Settings:
|
|
-------------------------
|
|
Trace Settings
|
|
|
|
Peak Memory Usage: 668 MB
|
|
|
|
|
|
|