You've already forked gitified_old_clb_svn
362 lines
127 KiB
XML
362 lines
127 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE twReport [
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<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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twDebug*, twFoot?, twClientInfo?)>
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<!ATTLIST twReport version CDATA "10,4">
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<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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<!ELEMENT twExecVer (#PCDATA)>
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<!ELEMENT twCopyright (#PCDATA)>
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<!ELEMENT twCmdLine (#PCDATA)>
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<!ELEMENT twDesign (#PCDATA)>
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<!ELEMENT twPCF (#PCDATA)>
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<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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<!ELEMENT twDevName (#PCDATA)>
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<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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<!ELEMENT twSpeedGrade (#PCDATA)>
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<!ELEMENT twSpeedVer (#PCDATA)>
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<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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<!ELEMENT twItemLimit (#PCDATA)>
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<!ELEMENT twUnconst EMPTY>
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<!ELEMENT twUnconstLimit (#PCDATA)>
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<!ELEMENT twEnvVar EMPTY>
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<!ATTLIST twEnvVar name CDATA #REQUIRED>
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<!ATTLIST twEnvVar description CDATA #REQUIRED>
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<!ELEMENT twWarn (#PCDATA)>
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<!ELEMENT twInfo (#PCDATA)>
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<!ELEMENT twDebug (#PCDATA)>
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<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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<!ELEMENT twProc (#PCDATA)>
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<!ELEMENT twTemp (#PCDATA)>
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<!ELEMENT twVolt (#PCDATA)>
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<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twCycles (twSigConn+)>
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<!ATTLIST twCycles twNum CDATA #REQUIRED>
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<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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<!ELEMENT twSig (#PCDATA)>
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<!ELEMENT twDriver (#PCDATA)>
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<!ELEMENT twLoad (#PCDATA)>
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<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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<!ATTLIST twConst twConstType (NET |
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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PATH2SETUP |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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PATHBLOCK |
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OFFSET |
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OFFSETIN |
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OFFSETINCLOCK |
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UNCONSTOFFSETINCLOCK |
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OFFSETINDELAY |
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OFFSETINMOD |
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OFFSETOUT |
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OFFSETOUTCLOCK |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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<!ELEMENT twConstName (#PCDATA)>
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<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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<!ATTLIST twConstHead uID CDATA #IMPLIED>
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<!ELEMENT twItemCnt (#PCDATA)>
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<!ELEMENT twErrCnt (#PCDATA)>
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<!ELEMENT twErrCntEndPt (#PCDATA)>
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<!ELEMENT twErrCntSetup (#PCDATA)>
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<!ELEMENT twErrCntHold (#PCDATA)>
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<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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<!ELEMENT twEndPtCnt (#PCDATA)>
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<!ELEMENT twPathErrCnt (#PCDATA)>
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<!ELEMENT twMinPer (#PCDATA) >
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<!ELEMENT twFootnote EMPTY>
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<!ATTLIST twFootnote number CDATA #REQUIRED>
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<!ELEMENT twMaxDel (#PCDATA)>
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<!ELEMENT twMaxFreq (#PCDATA)>
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<!ELEMENT twMinOff (#PCDATA)>
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<!ELEMENT twMaxOff (#PCDATA)>
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<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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<!ELEMENT twTIGName (#PCDATA)>
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<!ELEMENT twInstantiated (#PCDATA)>
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<!ELEMENT twBlocked (#PCDATA)>
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<!ELEMENT twRacePathRpt (twRacePath+)>
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<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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twSimpleMinPath CDATA #IMPLIED>
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<!ELEMENT twTotDel (#PCDATA)>
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<!ELEMENT twSrc (#PCDATA)>
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
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<!ELEMENT twDest (#PCDATA)>
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<!ATTLIST twDest BELType CDATA #IMPLIED>
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<!ELEMENT twDel (#PCDATA)>
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<!ELEMENT twSUTime (#PCDATA)>
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<!ELEMENT twTotPathDel (#PCDATA)>
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<!ELEMENT twClkSkew (#PCDATA)>
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<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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<!ELEMENT twSlack (#PCDATA)>
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<!ELEMENT twDelConst (#PCDATA)>
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<!ELEMENT tw2Phase EMPTY>
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<!ELEMENT twClkUncert (#PCDATA)>
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<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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<!ELEMENT twPathRptBanner (#PCDATA)>
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<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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<!ELEMENT twOff (#PCDATA)>
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<!ELEMENT twGuaranteed EMPTY>
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<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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<!ELEMENT twClkDel (#PCDATA)>
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<!ELEMENT twClkSrc (#PCDATA)>
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<!ELEMENT twClkDest (#PCDATA)>
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<!ELEMENT twGuarInSetup (#PCDATA)>
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<!ELEMENT twOffSrc (#PCDATA)>
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<!ELEMENT twOffDest (#PCDATA)>
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<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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<!ELEMENT twDataDel (#PCDATA)>
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<!ELEMENT twDataSrc (#PCDATA)>
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<!ELEMENT twDataDest (#PCDATA)>
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<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twLogLvls (#PCDATA)>
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<!ELEMENT twSrcSite (#PCDATA)>
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<!ELEMENT twSrcClk (#PCDATA)>
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<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
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<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
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<!ELEMENT twDelInfo (#PCDATA)>
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<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twSite (#PCDATA)>
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<!ELEMENT twDelType (#PCDATA)>
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<!ELEMENT twFanCnt (#PCDATA)>
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<!ELEMENT twComp (#PCDATA)>
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<!ELEMENT twNet (#PCDATA)>
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<!ELEMENT twBEL (#PCDATA)>
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<!ELEMENT twLogDel (#PCDATA)>
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<!ELEMENT twRouteDel (#PCDATA)>
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<!ELEMENT twDestClk (#PCDATA)>
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<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPctLog (#PCDATA)>
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<!ELEMENT twPctRoute (#PCDATA)>
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<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
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<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
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<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
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<!ELEMENT twTimeConst (#PCDATA)>
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<!ELEMENT twAbsSlack (#PCDATA)>
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<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
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<!ELEMENT twSkew (#PCDATA)>
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<!ELEMENT twDetNet (twNetDel*)>
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<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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<!ELEMENT twNetDelInfo (#PCDATA)>
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<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twDetSkewNet (twNetSkew*)>
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<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
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<!ELEMENT twClkSkewLimit EMPTY>
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<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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<!ELEMENT twConstRollupTable (twConstRollup*)>
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<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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<!ELEMENT twConstRollup EMPTY>
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<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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<!ELEMENT twConstList (twConstListItem)*>
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<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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<!ELEMENT twNotMet EMPTY>
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<!ELEMENT twReqVal (#PCDATA)>
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<!ELEMENT twActVal (#PCDATA)>
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<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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<!ELEMENT twConstStats (twConstName)>
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<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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<!ATTLIST twConstStats twActual CDATA #IMPLIED>
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<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
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<!ELEMENT twConstData EMPTY>
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<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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<!ELEMENT twTimeGrpName (#PCDATA)>
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<!ELEMENT twCompList (twCompName+)>
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<!ELEMENT twCompName (#PCDATA)>
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<!ELEMENT twSigList (twSigName+)>
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<!ELEMENT twSigName (#PCDATA)>
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<!ELEMENT twBELList (twBELName+)>
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<!ELEMENT twBELName (#PCDATA)>
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<!ELEMENT twBlockList (twBlockName+)>
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<!ELEMENT twBlockName (#PCDATA)>
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<!ELEMENT twMacList (twMacName+)>
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<!ELEMENT twMacName (#PCDATA)>
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<!ELEMENT twPinList (twPinName+)>
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<!ELEMENT twPinName (#PCDATA)>
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<!ELEMENT twUnmetConstCnt (#PCDATA)>
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<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
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<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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<!ELEMENT twSU2ClkTime (#PCDATA)>
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<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twH2ClkTime (#PCDATA)>
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<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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<!ELEMENT twClk2Pad (twDest, twTime)>
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<!ELEMENT twTime (#PCDATA)>
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<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
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<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
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<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
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<!ELEMENT twClk2Out EMPTY>
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<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
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<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
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<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
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<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
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<!ELEMENT twRiseRise (#PCDATA)>
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<!ELEMENT twFallRise (#PCDATA)>
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<!ELEMENT twRiseFall (#PCDATA)>
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<!ELEMENT twFallFall (#PCDATA)>
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<!ELEMENT twPad2PadList (twPad2Pad+)>
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<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
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<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
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<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
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<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
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<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
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<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
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<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffOutTblRow EMPTY>
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<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
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<!ELEMENT twNonDedClk (#PCDATA)>
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<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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<!ELEMENT twScore (#PCDATA)>
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<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
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<!ELEMENT twPathCnt (#PCDATA)>
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<!ELEMENT twNetCnt (#PCDATA)>
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<!ELEMENT twConnCnt (#PCDATA)>
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<!ELEMENT twPct (#PCDATA)>
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<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
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<!ELEMENT twMaxCombDel (#PCDATA)>
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<!ELEMENT twMaxFromToDel (#PCDATA)>
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<!ELEMENT twMaxNetDel (#PCDATA)>
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<!ELEMENT twMaxNetSkew (#PCDATA)>
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<!ELEMENT twMaxInAfterClk (#PCDATA)>
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<!ELEMENT twMinInBeforeClk (#PCDATA)>
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<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
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<twReport><twHead anchorID="1"><twExecVer>Release 14.2 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml fpga.twx fpga.ncd -o fpga.twr fpga.pcf
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</twCmdLine><twDesign>fpga.ncd</twDesign><twDesignPath>fpga.ncd</twDesignPath><twPCF>fpga.pcf</twPCF><twPcfPath>fpga.pcf</twPcfPath><twDevInfo arch="kintex7" pkg="ffg900"><twDevName>xc7k325t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRELIMINARY 1.06 2012-07-14</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINLOWPULSE" name="Tmmcmpw_CLKIN1_100_150" slack="4.000" period="8.000" constraintValue="4.000" deviceLimit="2.000" physResource="u1/mmcm_adv_inst/CLKIN1" logResource="u1/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X0Y1.CLKIN1" clockNet="u1/clkin1"/><twPinLimit anchorID="8" type="MINHIGHPULSE" name="Tmmcmpw_CLKIN1_100_150" slack="4.000" period="8.000" constraintValue="4.000" deviceLimit="2.000" physResource="u1/mmcm_adv_inst/CLKIN1" logResource="u1/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X0Y1.CLKIN1" clockNet="u1/clkin1"/><twPinLimit anchorID="9" type="MINPERIOD" name="Tibiper" slack="6.592" period="8.000" constraintValue="8.000" deviceLimit="1.408" freqLimit="710.227" physResource="u5/I" logResource="u5/I" locationPin="IBUFDS_GTE2_X0Y4.I" clockNet="ClkI_p_IBUF"/></twPinLimitRpt></twConst><twConst anchorID="10" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;</twConstName><twItemCnt>1696795</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>13209</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>12.252</twMinPer></twConstHead><twPathRptBanner iPaths="22" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (SLICE_X36Y183.C5), 22 paths
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</twPathRptBanner><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.937</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twTotPathDel>2.635</twTotPathDel><twClkSkew dest = "1.149" src = "1.378">0.229</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.129" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.199</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X54Y127.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X54Y127.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<7></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.069</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<7></twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twBEL></twPathDel><twLogDel>0.311</twLogDel><twRouteDel>2.324</twRouteDel><twTotDel>2.635</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>11.8</twPctLog><twPctRoute>88.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>11.976</twSlack><twSrc BELType="FF">u0/u0/inst_was_busy</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twTotPathDel>3.654</twTotPathDel><twClkSkew dest = "1.044" src = "1.338">0.294</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.135" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.076</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u0/inst_was_busy</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X42Y148.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X42Y148.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>u0/u0/inst_was_busy</twComp><twBEL>u0/u0/inst_was_busy</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y158.C1</twSite><twDelType>net</twDelType><twFanCnt>44</twFanCnt><twDelInfo twEdge="twRising">1.194</twDelInfo><twComp>u0/u0/inst_was_busy</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y158.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.135</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<4></twComp><twBEL>u0/u0/mux5711</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y177.A1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">0.919</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<3></twComp></twPathDel><twPathDel><twSite>SLICE_X23Y177.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/_n0073_inv</twComp><twBEL>u0/u9/crossbar/master_oe[1]_adr<3>1</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.B2</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">0.797</twDelInfo><twComp>u0/secbar_master_o[1]_adr<3></twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twBEL></twPathDel><twLogDel>0.489</twLogDel><twRouteDel>3.165</twRouteDel><twTotDel>3.654</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.4</twPctLog><twPctRoute>86.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>12.109</twSlack><twSrc BELType="FF">u0/u0/inst_addr_reg_3</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twTotPathDel>3.519</twTotPathDel><twClkSkew dest = "1.044" src = "1.340">0.296</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.135" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.076</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u0/inst_addr_reg_3</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X39Y145.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X39Y145.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.223</twDelInfo><twComp>u0/u0/inst_addr_reg<5></twComp><twBEL>u0/u0/inst_addr_reg_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y158.C3</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.091</twDelInfo><twComp>u0/u0/inst_addr_reg<3></twComp></twPathDel><twPathDel><twSite>SLICE_X22Y158.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.139</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<4></twComp><twBEL>u0/u0/mux5711</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y177.A1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">0.919</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<3></twComp></twPathDel><twPathDel><twSite>SLICE_X23Y177.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/_n0073_inv</twComp><twBEL>u0/u9/crossbar/master_oe[1]_adr<3>1</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.B2</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">0.797</twDelInfo><twComp>u0/secbar_master_o[1]_adr<3></twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2911</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux291</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twBEL></twPathDel><twLogDel>0.457</twLogDel><twRouteDel>3.062</twRouteDel><twTotDel>3.519</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.0</twPctLog><twPctRoute>87.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7 (SLICE_X36Y183.C3), 1 path
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</twPathRptBanner><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.050</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twTotPathDel>2.518</twTotPathDel><twClkSkew dest = "1.149" src = "1.382">0.233</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.129" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.199</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X50Y119.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X50Y119.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc4<7></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y183.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.250</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc4<7></twComp></twPathDel><twPathDel><twSite>SLICE_X36Y183.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<8></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2912</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_7</twBEL></twPathDel><twLogDel>0.268</twLogDel><twRouteDel>2.250</twRouteDel><twTotDel>2.518</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>10.6</twPctLog><twPctRoute>89.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="22" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4 (SLICE_X37Y180.D5), 22 paths
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</twPathRptBanner><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.350</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twTotPathDel>2.222</twTotPathDel><twClkSkew dest = "1.147" src = "1.376">0.229</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.129" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.199</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X54Y126.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X54Y126.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.grdc1.rdc/rd_dc_i_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.685</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/rtdc3<4></twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.243</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261</twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">-0.008</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twBEL></twPathDel><twLogDel>0.294</twLogDel><twRouteDel>1.928</twRouteDel><twTotDel>2.222</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.2</twPctLog><twPctRoute>86.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>12.048</twSlack><twSrc BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twTotPathDel>3.579</twTotPathDel><twClkSkew dest = "1.042" src = "1.339">0.297</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.135" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.076</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X39Y142.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X39Y142.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.223</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o<2></twComp><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y156.C2</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">1.141</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o<2></twComp></twPathDel><twPathDel><twSite>SLICE_X23Y156.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.139</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<5></twComp><twBEL>u0/u0/mux5411</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y176.B5</twSite><twDelType>net</twDelType><twFanCnt>42</twFanCnt><twDelInfo twEdge="twRising">0.994</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<2></twComp></twPathDel><twPathDel><twSite>SLICE_X40Y176.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<19></twComp><twBEL>u0/u9/crossbar/master_oe[1]_adr<2>1</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.B2</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.761</twDelInfo><twComp>u0/secbar_master_o[1]_adr<2></twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.243</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261</twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">-0.008</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twBEL></twPathDel><twLogDel>0.440</twLogDel><twRouteDel>3.139</twRouteDel><twTotDel>3.579</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>12.3</twPctLog><twPctRoute>87.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>12.064</twSlack><twSrc BELType="FF">u0/u0/inst_was_busy</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twTotPathDel>3.564</twTotPathDel><twClkSkew dest = "1.042" src = "1.338">0.296</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.135" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.076</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>u0/u0/inst_was_busy</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X42Y148.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X42Y148.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>u0/u0/inst_was_busy</twComp><twBEL>u0/u0/inst_was_busy</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y156.C1</twSite><twDelType>net</twDelType><twFanCnt>44</twFanCnt><twDelInfo twEdge="twRising">1.090</twDelInfo><twComp>u0/u0/inst_was_busy</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y156.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.139</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<5></twComp><twBEL>u0/u0/mux5411</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y176.B5</twSite><twDelType>net</twDelType><twFanCnt>42</twFanCnt><twDelInfo twEdge="twRising">0.994</twDelInfo><twComp>u0/cbar_slave_i[1]_adr<2></twComp></twPathDel><twPathDel><twSite>SLICE_X40Y176.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<19></twComp><twBEL>u0/u9/crossbar/master_oe[1]_adr<2>1</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.B2</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.761</twDelInfo><twComp>u0/secbar_master_o[1]_adr<2></twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2611</twBEL></twPathDel><twPathDel><twSite>SLICE_X37Y180.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.243</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux261</twComp></twPathDel><twPathDel><twSite>SLICE_X37Y180.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">-0.008</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/mux2612</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/wb_dat_o_4</twBEL></twPathDel><twLogDel>0.476</twLogDel><twRouteDel>3.088</twRouteDel><twTotDel>3.564</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.4</twPctLog><twPctRoute>86.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30 (SLICE_X20Y99.A4), 1 path
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</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.040</twSlack><twSrc BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twSrc><twDest BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30</twDest><twTotPathDel>0.306</twTotPathDel><twClkSkew dest = "0.795" src = "0.529">-0.266</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twSrc><twDest BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y106.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X23Y106.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.100</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<5></twComp><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twFalling">0.265</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<4></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y99.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.059</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result<31></twComp><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/Sh1581</twBEL><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_30</twBEL></twPathDel><twLogDel>0.041</twLogDel><twRouteDel>0.265</twRouteDel><twTotDel>0.306</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.4</twPctLog><twPctRoute>86.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31 (SLICE_X20Y99.B4), 1 path
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</twPathRptBanner><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.040</twSlack><twSrc BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twSrc><twDest BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31</twDest><twTotPathDel>0.306</twTotPathDel><twClkSkew dest = "0.795" src = "0.529">-0.266</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twSrc><twDest BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y106.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X23Y106.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.100</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<5></twComp><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y99.B4</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twFalling">0.265</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/operand_1_x<4></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y99.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.059</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result<31></twComp><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/Sh1591</twBEL><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/shifter/right_shift_result_31</twBEL></twPathDel><twLogDel>0.041</twLogDel><twRouteDel>0.265</twRouteDel><twTotDel>0.306</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.4</twPctLog><twPctRoute>86.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11 (SLICE_X18Y149.D6), 1 path
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</twPathRptBanner><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.048</twSlack><twSrc BELType="FF">u0/u1/crossbar/matrix_old_0_0</twSrc><twDest BELType="FF">u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11</twDest><twTotPathDel>0.315</twTotPathDel><twClkSkew dest = "0.796" src = "0.529">-0.267</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u1/crossbar/matrix_old_0_0</twSrc><twDest BELType='FF'>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y154.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X23Y154.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.100</twDelInfo><twComp>u0/u1/crossbar/matrix_old_0<3></twComp><twBEL>u0/u1/crossbar/matrix_old_0_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y149.D6</twSite><twDelType>net</twDelType><twFanCnt>76</twFanCnt><twDelInfo twEdge="twFalling">0.274</twDelInfo><twComp>u0/u1/crossbar/matrix_old_0<0></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y149.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.059</twDelInfo><twComp>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m<11></twComp><twBEL>u0/u1/crossbar/slave_o[0]_dat<11>1</twBEL><twBEL>u0/u0/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_store_unit/wb_data_m_11</twBEL></twPathDel><twLogDel>0.041</twLogDel><twRouteDel>0.274</twRouteDel><twTotDel>0.315</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">clk_62_5_o</twDestClk><twPctLog>13.0</twPctLog><twPctRoute>87.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="31"><twPinLimitBanner>Component Switching Limit Checks: TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="32" type="MINPERIOD" name="Tmmcmper_CLKOUT(Foutmax)" slack="2.929" period="4.000" constraintValue="4.000" deviceLimit="1.071" freqLimit="933.707" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKOUT0" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKOUT0" locationPin="MMCME2_ADV_X1Y2.CLKOUT0" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout0"/><twPinLimit anchorID="33" type="MINLOWPULSE" name="Tmmcmpw_CLKIN1_50_100" slack="10.000" period="16.000" constraintValue="8.000" deviceLimit="3.000" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X1Y2.CLKIN1" clockNet="clk_62_5_o"/><twPinLimit anchorID="34" type="MINHIGHPULSE" name="Tmmcmpw_CLKIN1_50_100" slack="10.000" period="16.000" constraintValue="8.000" deviceLimit="3.000" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X1Y2.CLKIN1" clockNet="clk_62_5_o"/></twPinLimitRpt></twConst><twConst anchorID="35" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0" TS_u1_clkout0 / 4 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.334</twMinPer></twConstHead><twPinLimitRpt anchorID="36"><twPinLimitBanner>Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = PERIOD TIMEGRP
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0"
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TS_u1_clkout0 / 4 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="37" type="MINLOWPULSE" name="Tmmcmpw_CLKIN1_250_300" slack="1.666" period="4.000" constraintValue="2.000" deviceLimit="1.167" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X0Y0.CLKIN1" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk0_in"/><twPinLimit anchorID="38" type="MINHIGHPULSE" name="Tmmcmpw_CLKIN1_250_300" slack="1.666" period="4.000" constraintValue="2.000" deviceLimit="1.167" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/mmcm_adv_inst/CLKIN1" locationPin="MMCME2_ADV_X0Y0.CLKIN1" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk0_in"/><twPinLimit anchorID="39" type="MINPERIOD" name="Tbcper_I(Fmax)" slack="2.592" period="4.000" constraintValue="4.000" deviceLimit="1.408" freqLimit="710.227" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf/I0" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout1_buf/I0" locationPin="BUFGCTRL_X0Y3.I0" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm250/clkout0"/></twPinLimitRpt></twConst><twConst anchorID="40" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1" TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.408</twMinPer></twConstHead><twPinLimitRpt anchorID="41"><twPinLimitBanner>Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PERIOD TIMEGRP
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1"
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TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1
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ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="42" type="MINPERIOD" name="Tbcper_I(Fmax)" slack="2.592" period="4.000" constraintValue="4.000" deviceLimit="1.408" freqLimit="710.227" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf/I0" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout2_buf/I0" locationPin="BUFGCTRL_X0Y2.I0" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/dcm2/clkout1"/></twPinLimitRpt></twConst><twConst anchorID="43" twConstType="PERIOD" ><twConstHead uID="5"><twConstName UCFConstName="" ScopeName="">TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0" TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;</twConstName><twItemCnt>77861</twItemCnt><twErrCntSetup>131</twErrCntSetup><twErrCntEndPt>131</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>4367</twEndPtCnt><twPathErrCnt>4688</twPathErrCnt><twMinPer>5.473</twMinPer></twConstHead><twPathRptBanner iPaths="185" iCriticalPaths="107" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19 (SLICE_X9Y122.D6), 185 paths
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</twPathRptBanner><twPathRpt anchorID="44"><twConstPath anchorID="45" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.473</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twTotPathDel>5.392</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.D6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.496</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.167</twRouteDel><twTotDel>5.392</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>41.3</twPctLog><twPctRoute>58.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="46"><twConstPath anchorID="47" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.473</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twTotPathDel>5.392</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.D6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.496</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.167</twRouteDel><twTotDel>5.392</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>41.3</twPctLog><twPctRoute>58.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="48"><twConstPath anchorID="49" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.395</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twTotPathDel>5.314</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO20</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.712</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.D6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.496</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_19</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.089</twRouteDel><twTotDel>5.314</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>41.9</twPctLog><twPctRoute>58.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="185" iCriticalPaths="106" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29 (SLICE_X9Y122.C6), 185 paths
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</twPathRptBanner><twPathRpt anchorID="50"><twConstPath anchorID="51" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.451</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twTotPathDel>5.370</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.C6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.145</twRouteDel><twTotDel>5.370</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="52"><twConstPath anchorID="53" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.451</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twTotPathDel>5.370</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.C6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.145</twRouteDel><twTotDel>5.370</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="54"><twConstPath anchorID="55" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.373</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twTotPathDel>5.292</twTotPathDel><twClkSkew dest = "0.609" src = "0.621">0.012</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO20</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.712</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y122.C6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y122.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<19></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_29</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.067</twRouteDel><twTotDel>5.292</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>42.0</twPctLog><twPctRoute>58.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="185" iCriticalPaths="106" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4 (SLICE_X9Y119.A6), 185 paths
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</twPathRptBanner><twPathRpt anchorID="56"><twConstPath anchorID="57" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.379</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twTotPathDel>5.302</twTotPathDel><twClkSkew dest = "0.613" src = "0.621">0.008</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.406</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y119.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.077</twRouteDel><twTotDel>5.302</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>42.0</twPctLog><twPctRoute>58.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="58"><twConstPath anchorID="59" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.379</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twTotPathDel>5.302</twTotPathDel><twClkSkew dest = "0.613" src = "0.621">0.008</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO16</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.790</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><29></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.406</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y119.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>3.077</twRouteDel><twTotDel>5.302</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>42.0</twPctLog><twPctRoute>58.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="60"><twConstPath anchorID="61" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.301</twSlack><twSrc BELType="RAM">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twTotPathDel>5.224</twTotPathDel><twClkSkew dest = "0.613" src = "0.621">0.008</twClkSkew><twDelConst>4.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.119" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.069</twClkUncert><twDetPath maxSiteLen="20" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twDest><twLogLvls>6</twLogLvls><twSrcSite>RAMB36_X2Y21.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>RAMB36_X2Y21.DOBDO20</twSite><twDelType>Trcko_DOB</twDelType><twDelInfo twEdge="twRising">1.800</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y110.C2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.712</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/evnt<1><33></twComp></twPathDel><twPathDel><twSite>SLICE_X51Y110.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.244</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21_G</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.629</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o21</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twBEL></twPathDel><twPathDel><twSite>SLICE_X49Y113.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp></twPathDel><twPathDel><twSite>SLICE_X49Y113.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o22</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y117.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.791</twDelInfo><twComp>N488</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y117.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3-In111</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o24</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.311</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel[0]_empty[0]_OR_2906_o</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y119.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<20></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y119.A6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">0.406</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0397_inv1_rstpot</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y119.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.009</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel<5></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4_dpot</twBEL><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/channel_4</twBEL></twPathDel><twLogDel>2.225</twLogDel><twRouteDel>2.999</twRouteDel><twTotDel>5.224</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>42.6</twPctLog><twPctRoute>57.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
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TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;
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</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6 (SLICE_X60Y98.CX), 1 path
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</twPathRptBanner><twPathRpt anchorID="62"><twConstPath anchorID="63" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.008</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6</twDest><twTotPathDel>0.271</twTotPathDel><twClkSkew dest = "0.747" src = "0.484">-0.263</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X56Y102.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X56Y102.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.118</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<1><7></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X60Y98.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<1><6></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X60Y98.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.047</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<2><9></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_6</twBEL></twPathDel><twLogDel>0.071</twLogDel><twRouteDel>0.200</twRouteDel><twTotDel>0.271</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>26.2</twPctLog><twPctRoute>73.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="7" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0 (SLICE_X18Y116.CE), 7 paths
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</twPathRptBanner><twPathRpt anchorID="64"><twConstPath anchorID="65" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.030</twSlack><twSrc BELType="FF">u7/u1/O_n</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twTotPathDel>0.478</twTotPathDel><twClkSkew dest = "0.856" src = "0.670">-0.186</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.254" fPhaseErr="0.129" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.262</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u7/u1/O_n</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X7Y115.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X7Y115.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.100</twDelInfo><twComp>u7/u1/O_n</twComp><twBEL>u7/u1/O_n</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C5</twSite><twDelType>net</twDelType><twFanCnt>245</twFanCnt><twDelInfo twEdge="twRising">0.326</twDelInfo><twComp>u7/u1/O_n</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twBEL></twPathDel><twLogDel>0.098</twLogDel><twRouteDel>0.380</twRouteDel><twTotDel>0.478</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>20.5</twPctLog><twPctRoute>79.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="66"><twConstPath anchorID="67" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.323</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twTotPathDel>0.354</twTotPathDel><twClkSkew dest = "0.363" src = "0.332">-0.031</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X11Y117.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X11Y117.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.100</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C6</twSite><twDelType>net</twDelType><twFanCnt>41</twFanCnt><twDelInfo twEdge="twRising">0.202</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twBEL></twPathDel><twLogDel>0.098</twLogDel><twRouteDel>0.256</twRouteDel><twTotDel>0.354</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>27.7</twPctLog><twPctRoute>72.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="68"><twConstPath anchorID="69" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.473</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twTotPathDel>0.504</twTotPathDel><twClkSkew dest = "0.363" src = "0.332">-0.031</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X12Y117.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X12Y117.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C3</twSite><twDelType>net</twDelType><twFanCnt>46</twFanCnt><twDelInfo twEdge="twRising">0.334</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_0</twBEL></twPathDel><twLogDel>0.116</twLogDel><twRouteDel>0.388</twRouteDel><twTotDel>0.504</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>23.0</twPctLog><twPctRoute>77.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="7" iCriticalPaths="0" sType="EndPoint">Paths for end point u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1 (SLICE_X18Y116.CE), 7 paths
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</twPathRptBanner><twPathRpt anchorID="70"><twConstPath anchorID="71" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.030</twSlack><twSrc BELType="FF">u7/u1/O_n</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twTotPathDel>0.478</twTotPathDel><twClkSkew dest = "0.856" src = "0.670">-0.186</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.254" fPhaseErr="0.129" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.262</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u7/u1/O_n</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X7Y115.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_62_5_o</twSrcClk><twPathDel><twSite>SLICE_X7Y115.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.100</twDelInfo><twComp>u7/u1/O_n</twComp><twBEL>u7/u1/O_n</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C5</twSite><twDelType>net</twDelType><twFanCnt>245</twFanCnt><twDelInfo twEdge="twRising">0.326</twDelInfo><twComp>u7/u1/O_n</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twBEL></twPathDel><twLogDel>0.098</twLogDel><twRouteDel>0.380</twRouteDel><twTotDel>0.478</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>20.5</twPctLog><twPctRoute>79.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="72"><twConstPath anchorID="73" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.323</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twTotPathDel>0.354</twTotPathDel><twClkSkew dest = "0.363" src = "0.332">-0.031</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X11Y117.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X11Y117.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.100</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd3</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C6</twSite><twDelType>net</twDelType><twFanCnt>41</twFanCnt><twDelInfo twEdge="twRising">0.202</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twBEL></twPathDel><twLogDel>0.098</twLogDel><twRouteDel>0.256</twRouteDel><twTotDel>0.354</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>27.7</twPctLog><twPctRoute>72.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="74"><twConstPath anchorID="75" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.473</twSlack><twSrc BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twSrc><twDest BELType="FF">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twTotPathDel>0.504</twTotPathDel><twClkSkew dest = "0.363" src = "0.332">-0.031</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twSrc><twDest BELType='FF'>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X12Y117.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twSrcClk><twPathDel><twSite>SLICE_X12Y117.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.118</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.C3</twSite><twDelType>net</twDelType><twFanCnt>46</twFanCnt><twDelInfo twEdge="twRising">0.334</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/state_down_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y116.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv1</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y116.CE</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.054</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/_n0596_inv</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X18Y116.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.030</twDelInfo><twComp>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download<1></twComp><twBEL>u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/download_1</twBEL></twPathDel><twLogDel>0.116</twLogDel><twRouteDel>0.388</twRouteDel><twTotDel>0.504</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="4.000">u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0</twDestClk><twPctLog>23.0</twPctLog><twPctRoute>77.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="76"><twPinLimitBanner>Component Switching Limit Checks: TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP
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"u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0"
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TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="77" type="MINPERIOD" name="Trper_CLKA" slack="2.161" period="4.000" constraintValue="4.000" deviceLimit="1.839" freqLimit="543.774" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK" locationPin="RAMB18_X2Y47.CLKARDCLK" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0"/><twPinLimit anchorID="78" type="MINPERIOD" name="Trper_CLKA" slack="2.161" period="4.000" constraintValue="4.000" deviceLimit="1.839" freqLimit="543.774" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKBWRCLK" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[1].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKBWRCLK" locationPin="RAMB18_X2Y47.CLKBWRCLK" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0"/><twPinLimit anchorID="79" type="MINPERIOD" name="Trper_CLKA" slack="2.161" period="4.000" constraintValue="4.000" deviceLimit="1.839" freqLimit="543.774" physResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK" logResource="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/all_channels[0].channel_tdc/c_fifo_tdc/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKARDCLK" locationPin="RAMB18_X2Y46.RDCLK" clockNet="u0/u11/U_Wrapped_tdc/Wrapped_tdc/U_Mux_tdc/clk_0"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="80"><twConstRollup name="TS_ClkI_p" fullName="TS_ClkI_p = PERIOD TIMEGRP "ClkI_p" 8 ns HIGH 50%;" type="origin" depth="0" requirement="8.000" prefType="period" actual="4.000" actualRollup="10.946" errors="0" errorRollup="131" items="0" itemsRollup="1774656"/><twConstRollup name="TS_u1_clkout0" fullName="TS_u1_clkout0 = PERIOD TIMEGRP "u1_clkout0" TS_ClkI_p / 0.5 HIGH 50%;" type="child" depth="1" requirement="16.000" prefType="period" actual="12.252" actualRollup="21.892" errors="0" errorRollup="131" items="1696795" itemsRollup="77861"/><twConstRollup name="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0" fullName="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0" TS_u1_clkout0 / 4 HIGH 50%;" type="child" depth="2" requirement="4.000" prefType="period" actual="2.334" actualRollup="5.473" errors="0" errorRollup="131" items="0" itemsRollup="77861"/><twConstRollup name="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1" fullName="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout1" TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 PHASE 1 ns HIGH 50%;" type="child" depth="3" requirement="4.000" prefType="period" actual="1.408" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0" fullName="TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0 = PERIOD TIMEGRP "u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm2_clkout0" TS_u0_u11_U_Wrapped_tdc_Wrapped_tdc_U_Mux_tdc_dcm250_clkout0 HIGH 50%;" type="child" depth="3" requirement="4.000" prefType="period" actual="5.473" actualRollup="N/A" errors="131" errorRollup="0" items="77861" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="81">1</twUnmetConstCnt><twDataSheet anchorID="82" twNameLen="15"><twClk2SUList anchorID="83" twDestWidth="6"><twDest>ClkI_n</twDest><twClk2SU><twSrc>ClkI_n</twSrc><twRiseRise>8.433</twRiseRise></twClk2SU><twClk2SU><twSrc>ClkI_p</twSrc><twRiseRise>8.433</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="84" twDestWidth="6"><twDest>ClkI_p</twDest><twClk2SU><twSrc>ClkI_n</twSrc><twRiseRise>8.433</twRiseRise></twClk2SU><twClk2SU><twSrc>ClkI_p</twSrc><twRiseRise>8.433</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="85"><twErrCnt>131</twErrCnt><twScore>65286</twScore><twSetupScore>65286</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>1774656</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>26189</twConnCnt></twConstCov><twStats anchorID="86"><twMinPer>12.252</twMinPer><twFootnote number="1" /><twMaxFreq>81.619</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Jul 19 19:16:58 2013 </twTimestamp></twFoot><twClientInfo anchorID="87"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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Peak Memory Usage: 668 MB
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</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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