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366 lines
24 KiB
XML
366 lines
24 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
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<files>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
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</file>
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</file>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="165"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="166"/>
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</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="167"/>
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</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="168"/>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="170"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="171"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="173"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="178"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
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</file>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="181"/>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="183"/>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="185"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="186"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="187"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
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</file>
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<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="188"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_date_rev_id/wb_date_rev_id.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_date_rev_id/xwb_date_rev_id.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="190"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/dcm_tdc_250.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/DRU.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/mux_tdc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="193"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/mydcm_phases.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="194"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/tdc_top.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/uart232.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="197"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="198"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/wb_tdc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="199"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/wrapped_mux_tdc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="200"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
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</file>
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<file xil_pn:name="../../modules/wishbone/wb_tdc/xwb_tdc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="201"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
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</file>
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<file xil_pn:name="../../../../WRPC/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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|
</file>
|
|
<file xil_pn:name="../../../../WRPC/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="203"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../WRPC/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="204"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../WRPC/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="205"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
|
|
</file>
|
|
<file xil_pn:name="../../ip_cores/cmp_sys_clk_pll.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
|
|
</file>
|
|
<file xil_pn:name="../../modules/lm32_2nd_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
|
|
</file>
|
|
<file xil_pn:name="../../top/fpga.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="208"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
|
|
</file>
|
|
<file xil_pn:name="../../modules/xwb_aes_empty.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
|
|
</file>
|
|
<file xil_pn:name="../../modules/aes_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
|
|
</file>
|
|
<file xil_pn:name="../../ip_cores/fifo.xco" xil_pn:type="FILE_COREGEN">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
|
</file>
|
|
<file xil_pn:name="../../modules/tdc_pkg.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
|
|
</file>
|
|
<file xil_pn:name="../../syn/syn_top/lm32_empty_memory.ldr" xil_pn:type="FILE_USERDOC"/>
|
|
<file xil_pn:name="../../syn/syn_top/fpga.ucf" xil_pn:type="FILE_UCF">
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
|
</file>
|
|
<file xil_pn:name="../../modules/wishbone/wb_tdc/tdc_wb.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../TestDesigns/multiboot/modules/wb_multiboot/multiboot.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../TestDesigns/multiboot/modules/wb_multiboot/multiboot_master_top.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../TestDesigns/multiboot/modules/wb_multiboot/wb_multiboot.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
|
|
</file>
|
|
<file xil_pn:name="../../../../TestDesigns/multiboot/modules/wb_multiboot/xwb_multiboot.vhd" xil_pn:type="FILE_VHDL">
|
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
|
|
</file>
|
|
<file xil_pn:name="../../ip_cores/fifo.xise" xil_pn:type="FILE_COREGENISE">
|
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
|
</file>
|
|
</files>
|
|
|
|
<properties>
|
|
<property xil_pn:name="Device" xil_pn:value="xc7k325t" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Kintex-7 KC705 Evaluation Platform" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fpga|a0" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/fpga.vhd" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fpga" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
|
<!-- -->
|
|
<!-- The following properties are for internal use only. These should not be modified.-->
|
|
<!-- -->
|
|
<property xil_pn:name="PROP_DesignName" xil_pn:value="fpga" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
|
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-08-01T19:51:23" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="51C8808720364A03A2E27EC80424981A" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
|
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
|
</properties>
|
|
|
|
<bindings/>
|
|
|
|
<libraries/>
|
|
|
|
<autoManagedFiles>
|
|
<!-- The following files are identified by `include statements in verilog -->
|
|
<!-- source files and are automatically managed by Project Navigator. -->
|
|
<!-- -->
|
|
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
|
<!-- project is analyzed based on files automatically identified as -->
|
|
<!-- include files. -->
|
|
<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
|
|
<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
|
|
<file xil_pn:name="../../../../WRPC/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
|
|
</autoManagedFiles>
|
|
|
|
</project>
|