peterj.nikhef.nl b95bb30216 The CLBv2 Proto arrived in A'dam and thus this is a version where the design can be implemented in the KC705 (with or without SoftPLL) and in the CLBv2-Proto. It was necessary to implement a "g_use_clbv2" to solve some KC705/CLBv2 differences and a "g_use_clbv2_proto" to circumvent the "PPS_P/N LVDS in a 3v3 IO bank issue". ...

KC705 design tested in real hardware (Ethernet + WR okay)
KC705_WithoutSoftPLL tested in real hardware
CLBv2 Proto (not tested yet) but bitfile made

2013-12-20 13:43:50 +00:00

..

doc

added scripts for Precision synthesys. generated bitfile is not fully functional (Pahse Tracking stays OFF)

2013-08-14 13:34:43 +00:00

sim/wrpc_demo

added scripts for Precision synthesys. generated bitfile is not fully functional (Pahse Tracking stays OFF)

2013-08-14 13:34:43 +00:00

syn

wrpc_demo wroks when synthesis is done with XST but fails when using Precision. Symptom: Servo state says "uninitialized"

2013-08-15 21:37:39 +00:00

top/wrpc_demo

The CLBv2 Proto arrived in A'dam and thus this is a version where the design can be implemented in the KC705 (with or without SoftPLL) and in the CLBv2-Proto. It was necessary to implement a "g_use_clbv2" to solve some KC705/CLBv2 differences and a "g_use_clbv2_proto" to circumvent the "PPS_P/N LVDS in a 3v3 IO bank issue".

2013-12-20 13:43:50 +00:00