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51 lines
843 B
Systemverilog
51 lines
843 B
Systemverilog
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interface IWishboneLink;
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parameter g_data_width = 32;
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parameter g_addr_width = 32;
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wire [g_addr_width - 1 : 0] adr;
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wire [g_data_width - 1 : 0] dat_o;
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wire [g_data_width - 1 : 0] dat_i;
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wire [(g_data_width/8)-1 : 0] sel;
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wire ack;
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wire stall;
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wire err;
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wire rty;
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wire cyc;
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wire stb;
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wire we;
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modport slave
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(
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output adr,
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output dat_o,
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input dat_i,
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output sel,
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output cyc,
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output stb,
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output we,
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input ack,
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input stall,
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input err,
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input rty
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);
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modport master
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(
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input adr,
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input dat_o,
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output dat_i,
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input sel,
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input cyc,
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input stb,
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input we,
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output ack,
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output stall,
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output err,
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output rty
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);
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endinterface // IWishboneLink
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