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78 lines
1.3 KiB
Systemverilog
78 lines
1.3 KiB
Systemverilog
//
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// Title : Software Wishbone master unit for testbenches
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//
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// File : wishbone_master_tb.v
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// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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// Created : Tue Mar 23 12:19:36 2010
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// Standard : Verilog 2001
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//
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`ifndef __IF_WB_DEFS_SV
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`define __IF_WB_DEFS_SV
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`include "simdrv_defs.sv"
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typedef enum
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{
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R_OK = 0,
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R_ERROR,
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R_RETRY
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} wb_cycle_result_t;
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typedef enum
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{
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CLASSIC = 0,
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PIPELINED = 1
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} wb_cycle_type_t;
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typedef struct {
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uint64_t a;
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uint64_t d;
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bit[7:0] sel;
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int size;
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} wb_xfer_t;
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typedef struct {
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int rw;
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wb_cycle_type_t ctype;
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wb_xfer_t data[$];
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wb_cycle_result_t result;
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} wb_cycle_t;
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virtual class CWishboneAccessor;
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virtual function automatic int poll();
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return 0;
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endfunction // poll
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virtual task get(output wb_cycle_t xfer);
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endtask // get
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virtual task put(input wb_cycle_t xfer);
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endtask // put
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virtual function int idle();
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return 0;
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endfunction // idle
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virtual task clear(); endtask
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endclass // CWishboneAccessor
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int seed = 0;
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function automatic int probability_hit(real prob);
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real rand_val;
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rand_val = real'($dist_uniform(seed, 0, 1000)) / 1000.0;
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if(rand_val < prob)
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return 1;
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else
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return 0;
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endfunction // probability_hit
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`endif // `ifndef __IF_WB_DEFS_SV
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