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70 lines
2.6 KiB
Systemverilog
70 lines
2.6 KiB
Systemverilog
`define ADDR_MINIC_MCR 7'h0
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`define MINIC_MCR_TX_START_OFFSET 0
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`define MINIC_MCR_TX_START 32'h00000001
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`define MINIC_MCR_TX_IDLE_OFFSET 1
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`define MINIC_MCR_TX_IDLE 32'h00000002
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`define MINIC_MCR_TX_ERROR_OFFSET 2
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`define MINIC_MCR_TX_ERROR 32'h00000004
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`define MINIC_MCR_RX_READY_OFFSET 8
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`define MINIC_MCR_RX_READY 32'h00000100
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`define MINIC_MCR_RX_FULL_OFFSET 9
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`define MINIC_MCR_RX_FULL 32'h00000200
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`define MINIC_MCR_RX_EN_OFFSET 10
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`define MINIC_MCR_RX_EN 32'h00000400
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`define MINIC_MCR_TX_TS_READY_OFFSET 11
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`define MINIC_MCR_TX_TS_READY 32'h00000800
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`define MINIC_MCR_RX_CLASS_OFFSET 16
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`define MINIC_MCR_RX_CLASS 32'h00ff0000
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`define ADDR_MINIC_TX_ADDR 7'h4
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`define ADDR_MINIC_RX_ADDR 7'h8
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`define ADDR_MINIC_RX_SIZE 7'hc
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`define ADDR_MINIC_RX_AVAIL 7'h10
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`define ADDR_MINIC_TSR0 7'h14
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`define MINIC_TSR0_VALID_OFFSET 0
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`define MINIC_TSR0_VALID 32'h00000001
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`define MINIC_TSR0_PID_OFFSET 1
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`define MINIC_TSR0_PID 32'h0000003e
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`define MINIC_TSR0_FID_OFFSET 6
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`define MINIC_TSR0_FID 32'h003fffc0
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`define ADDR_MINIC_TSR1 7'h18
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`define MINIC_TSR1_TSVAL_OFFSET 0
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`define MINIC_TSR1_TSVAL 32'hffffffff
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`define ADDR_MINIC_DBGR 7'h1c
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`define MINIC_DBGR_IRQ_CNT_OFFSET 0
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`define MINIC_DBGR_IRQ_CNT 32'h00ffffff
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`define MINIC_DBGR_WB_IRQ_VAL_OFFSET 24
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`define MINIC_DBGR_WB_IRQ_VAL 32'h01000000
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`define ADDR_MINIC_MPROT 7'h20
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`define MINIC_MPROT_LO_OFFSET 0
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`define MINIC_MPROT_LO 32'h0000ffff
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`define MINIC_MPROT_HI_OFFSET 16
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`define MINIC_MPROT_HI 32'hffff0000
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`define ADDR_MINIC_EIC_IDR 7'h40
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`define MINIC_EIC_IDR_TX_OFFSET 0
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`define MINIC_EIC_IDR_TX 32'h00000001
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`define MINIC_EIC_IDR_RX_OFFSET 1
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`define MINIC_EIC_IDR_RX 32'h00000002
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`define MINIC_EIC_IDR_TXTS_OFFSET 2
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`define MINIC_EIC_IDR_TXTS 32'h00000004
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`define ADDR_MINIC_EIC_IER 7'h44
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`define MINIC_EIC_IER_TX_OFFSET 0
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`define MINIC_EIC_IER_TX 32'h00000001
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`define MINIC_EIC_IER_RX_OFFSET 1
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`define MINIC_EIC_IER_RX 32'h00000002
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`define MINIC_EIC_IER_TXTS_OFFSET 2
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`define MINIC_EIC_IER_TXTS 32'h00000004
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`define ADDR_MINIC_EIC_IMR 7'h48
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`define MINIC_EIC_IMR_TX_OFFSET 0
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`define MINIC_EIC_IMR_TX 32'h00000001
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`define MINIC_EIC_IMR_RX_OFFSET 1
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`define MINIC_EIC_IMR_RX 32'h00000002
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`define MINIC_EIC_IMR_TXTS_OFFSET 2
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`define MINIC_EIC_IMR_TXTS 32'h00000004
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`define ADDR_MINIC_EIC_ISR 7'h4c
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`define MINIC_EIC_ISR_TX_OFFSET 0
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`define MINIC_EIC_ISR_TX 32'h00000001
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`define MINIC_EIC_ISR_RX_OFFSET 1
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`define MINIC_EIC_ISR_RX 32'h00000002
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`define MINIC_EIC_ISR_TXTS_OFFSET 2
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`define MINIC_EIC_ISR_TXTS 32'h00000004
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