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42 lines
1.6 KiB
Verilog
42 lines
1.6 KiB
Verilog
`define ADDR_SPLL_CSR 6'h0
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`define SPLL_CSR_N_REF_OFFSET 0
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`define SPLL_CSR_N_REF 32'h0000003f
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`define SPLL_CSR_N_OUT_OFFSET 8
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`define SPLL_CSR_N_OUT 32'h00000700
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`define ADDR_SPLL_OCCR 6'h4
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`define SPLL_OCCR_OUT_EN_OFFSET 0
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`define SPLL_OCCR_OUT_EN 32'h000000ff
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`define SPLL_OCCR_AUX_LOCK_OFFSET 8
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`define SPLL_OCCR_AUX_LOCK 32'h0000ff00
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`define ADDR_SPLL_RCER 6'h8
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`define ADDR_SPLL_PER_HPLL 6'hc
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`define ADDR_SPLL_DAC_HPLL 6'h10
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`define ADDR_SPLL_DAC_MAIN 6'h14
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`define SPLL_DAC_MAIN_VALUE_OFFSET 0
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`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
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`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
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`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
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`define ADDR_SPLL_DEGLITCH_THR 6'h18
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`define ADDR_SPLL_EIC_IDR 6'h20
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`define SPLL_EIC_IDR_TAG_OFFSET 0
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`define SPLL_EIC_IDR_TAG 32'h00000001
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`define ADDR_SPLL_EIC_IER 6'h24
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`define SPLL_EIC_IER_TAG_OFFSET 0
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`define SPLL_EIC_IER_TAG 32'h00000001
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`define ADDR_SPLL_EIC_IMR 6'h28
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`define SPLL_EIC_IMR_TAG_OFFSET 0
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`define SPLL_EIC_IMR_TAG 32'h00000001
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`define ADDR_SPLL_EIC_ISR 6'h2c
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`define SPLL_EIC_ISR_TAG_OFFSET 0
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`define SPLL_EIC_ISR_TAG 32'h00000001
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`define ADDR_SPLL_TRR_R0 6'h30
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`define SPLL_TRR_R0_VALUE_OFFSET 0
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`define SPLL_TRR_R0_VALUE 32'h00ffffff
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`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
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`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
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`define SPLL_TRR_R0_DISC_OFFSET 31
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`define SPLL_TRR_R0_DISC 32'h80000000
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`define ADDR_SPLL_TRR_CSR 6'h34
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`define SPLL_TRR_CSR_EMPTY_OFFSET 17
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`define SPLL_TRR_CSR_EMPTY 32'h00020000
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