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88 lines
3.4 KiB
Systemverilog
88 lines
3.4 KiB
Systemverilog
`define ADDR_SPLL_CSR 7'h0
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`define SPLL_CSR_PER_SEL_OFFSET 0
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`define SPLL_CSR_PER_SEL 32'h0000003f
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`define SPLL_CSR_N_REF_OFFSET 8
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`define SPLL_CSR_N_REF 32'h00003f00
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`define SPLL_CSR_N_OUT_OFFSET 16
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`define SPLL_CSR_N_OUT 32'h00070000
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`define SPLL_CSR_PER_EN_OFFSET 19
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`define SPLL_CSR_PER_EN 32'h00080000
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`define ADDR_SPLL_ECCR 7'h4
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`define SPLL_ECCR_EXT_EN_OFFSET 0
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`define SPLL_ECCR_EXT_EN 32'h00000001
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`define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1
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`define SPLL_ECCR_EXT_SUPPORTED 32'h00000002
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`define SPLL_ECCR_ALIGN_EN_OFFSET 2
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`define SPLL_ECCR_ALIGN_EN 32'h00000004
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`define SPLL_ECCR_ALIGN_DONE_OFFSET 3
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`define SPLL_ECCR_ALIGN_DONE 32'h00000008
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`define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 4
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`define SPLL_ECCR_EXT_REF_PRESENT 32'h00000010
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`define ADDR_SPLL_DCCR 7'h8
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`define SPLL_DCCR_GATE_DIV_OFFSET 0
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`define SPLL_DCCR_GATE_DIV 32'h0000003f
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`define ADDR_SPLL_RCGER 7'hc
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`define SPLL_RCGER_GATE_SEL_OFFSET 0
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`define SPLL_RCGER_GATE_SEL 32'hffffffff
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`define ADDR_SPLL_OCCR 7'h10
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`define SPLL_OCCR_OUT_EN_OFFSET 0
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`define SPLL_OCCR_OUT_EN 32'h000000ff
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`define SPLL_OCCR_OUT_LOCK_OFFSET 8
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`define SPLL_OCCR_OUT_LOCK 32'h0000ff00
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`define ADDR_SPLL_RCER 7'h14
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`define ADDR_SPLL_OCER 7'h18
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`define ADDR_SPLL_PER_HPLL 7'h1c
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`define SPLL_PER_HPLL_ERROR_OFFSET 0
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`define SPLL_PER_HPLL_ERROR 32'h0000ffff
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`define SPLL_PER_HPLL_VALID_OFFSET 16
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`define SPLL_PER_HPLL_VALID 32'h00010000
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`define ADDR_SPLL_DAC_HPLL 7'h20
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`define ADDR_SPLL_DAC_MAIN 7'h24
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`define SPLL_DAC_MAIN_VALUE_OFFSET 0
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`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
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`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
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`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
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`define ADDR_SPLL_DEGLITCH_THR 7'h28
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`define ADDR_SPLL_DFR_SPLL 7'h2c
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`define SPLL_DFR_SPLL_VALUE_OFFSET 0
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`define SPLL_DFR_SPLL_VALUE 32'h7fffffff
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`define SPLL_DFR_SPLL_EOS_OFFSET 31
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`define SPLL_DFR_SPLL_EOS 32'h80000000
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`define ADDR_SPLL_CRR_IN 7'h30
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`define ADDR_SPLL_CRR_OUT 7'h34
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`define ADDR_SPLL_EIC_IDR 7'h40
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`define SPLL_EIC_IDR_TAG_OFFSET 0
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`define SPLL_EIC_IDR_TAG 32'h00000001
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`define ADDR_SPLL_EIC_IER 7'h44
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`define SPLL_EIC_IER_TAG_OFFSET 0
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`define SPLL_EIC_IER_TAG 32'h00000001
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`define ADDR_SPLL_EIC_IMR 7'h48
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`define SPLL_EIC_IMR_TAG_OFFSET 0
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`define SPLL_EIC_IMR_TAG 32'h00000001
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`define ADDR_SPLL_EIC_ISR 7'h4c
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`define SPLL_EIC_ISR_TAG_OFFSET 0
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`define SPLL_EIC_ISR_TAG 32'h00000001
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`define ADDR_SPLL_DFR_HOST_R0 7'h50
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`define SPLL_DFR_HOST_R0_VALUE_OFFSET 0
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`define SPLL_DFR_HOST_R0_VALUE 32'hffffffff
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`define ADDR_SPLL_DFR_HOST_R1 7'h54
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`define SPLL_DFR_HOST_R1_SEQ_ID_OFFSET 0
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`define SPLL_DFR_HOST_R1_SEQ_ID 32'h0000ffff
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`define ADDR_SPLL_DFR_HOST_CSR 7'h58
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`define SPLL_DFR_HOST_CSR_FULL_OFFSET 16
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`define SPLL_DFR_HOST_CSR_FULL 32'h00010000
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`define SPLL_DFR_HOST_CSR_EMPTY_OFFSET 17
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`define SPLL_DFR_HOST_CSR_EMPTY 32'h00020000
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`define SPLL_DFR_HOST_CSR_USEDW_OFFSET 0
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`define SPLL_DFR_HOST_CSR_USEDW 32'h00001fff
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`define ADDR_SPLL_TRR_R0 7'h5c
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`define SPLL_TRR_R0_VALUE_OFFSET 0
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`define SPLL_TRR_R0_VALUE 32'h00ffffff
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`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
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`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
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`define SPLL_TRR_R0_DISC_OFFSET 31
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`define SPLL_TRR_R0_DISC 32'h80000000
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`define ADDR_SPLL_TRR_CSR 7'h60
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`define SPLL_TRR_CSR_EMPTY_OFFSET 17
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`define SPLL_TRR_CSR_EMPTY 32'h00020000
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