You've already forked gitified_old_clb_svn
89 lines
1.9 KiB
Systemverilog
89 lines
1.9 KiB
Systemverilog
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`timescale 1ps/1ps
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// Clock/reset generator module for the TBI interface.
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module tbi_clock_rst_gen
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(
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output clk_ref_o,
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output clk_sys_o,
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output phy_rbclk_o,
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output rst_n_o);
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parameter g_rbclk_period = 8010;
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parameter g_refclk_period = 8000;
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parameter g_sysclk_period = 15900;
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reg refclk = 0, refclk2 = 0, rbclk = 0, rst_n = 0;
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always #(g_rbclk_period/2) rbclk <= ~rbclk;
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always #(g_refclk_period/2) refclk <= ~refclk;
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always #(g_sysclk_period/2) refclk2 <= ~refclk2;
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// always@(posedge refclk) refclk2 <= ~refclk2;
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initial begin repeat(10) @(posedge refclk2); rst_n = 1; end
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assign clk_ref_o = refclk;
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assign clk_sys_o = refclk2;
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assign phy_rbclk_o = rbclk;
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assign rst_n_o = rst_n;
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endmodule // tbi_clock_gen
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`timescale 1ns/1ps
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// Clock alignment FIFO for looping back the endpoint TX/RX path
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module tbi_loopback_fifo
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(
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input tx_clk_i,
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input rx_clk_i,
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input [9:0] tx_data_i,
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output reg [9:0] rx_data_o
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);
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parameter g_buf_size = 20000;
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parameter g_error_prob = 0;
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function automatic int probability_hit(int prob, int max_prob);
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int rand_val;
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rand_val = $random % (max_prob+1);
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if(rand_val < 0) rand_val = -rand_val;
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if(rand_val < prob)
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return 1;
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else
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return 0;
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endfunction // probability_hit
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reg[9:0] buffer[100000];
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int write_ptr, read_ptr, count;
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initial begin
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write_ptr = 0;
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read_ptr = 0;
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count = 0;
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end
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always@(posedge tx_clk_i) begin
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buffer[write_ptr] <= tx_data_i;
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count++;
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write_ptr++;
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end
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always@(posedge rx_clk_i) begin
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if(count == 0) begin
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$display("loopback FIFO underrun!");
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rx_data_o <= 0;
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end else begin
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if(probability_hit(g_error_prob, 1000))
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rx_data_o <= 'hfff;
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else
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rx_data_o <= buffer[read_ptr];
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read_ptr++;
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count--;
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end
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end
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endmodule
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