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59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
/*
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White Rabbit Softcore PLL (SoftPLL) - common definitions
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WARNING: These parameters must be in sync with the generics of the HDL instantiation of wr_softpll_ng.
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*/
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#include <stdio.h>
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#include "board.h"
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/* Reference clock frequency, in [Hz] */
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#define CLOCK_FREQ REF_CLOCK_FREQ_HZ
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/* Reference clock period, in picoseconds */
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#define CLOCK_PERIOD_PICOSECONDS REF_CLOCK_PERIOD_PS
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/* optional DMTD clock division to improve FPGA timing closure by avoiding
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clock nets directly driving FD inputs. Must be consistent with the
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g_divide_inputs_by_2 generic. */
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#ifdef SPEC_CLOCK
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#define DIVIDE_DMTD_CLOCKS_BY_2 1
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#else
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#define DIVIDE_DMTD_CLOCKS_BY_2 0
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#endif
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/* Number of bits in phase tags generated by the DMTDs. Used to sign-extend the tags.
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Corresponding VHDL generic: g_tag_bits. */
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#define TAG_BITS 22
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/* Helper PLL N divider (2**(-N) is the frequency offset). Must be big enough
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to offer reasonable PLL bandwidth, and small enough so the offset frequency fits
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within the tuning range of the helper oscillator. */
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#define HPLL_N 14
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/* Fractional bits in PI controller coefficients */
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#define PI_FRACBITS 12
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/* Max. allowed number of reference channels. Can be used to tweak memory usage. */
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#define MAX_CHAN_REF 1
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/* Max. allowed number of auxillary channels */
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#define MAX_CHAN_AUX 2
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/* Max. allowed number of phase trackers */
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#define MAX_PTRACKERS 1
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/* Number of bits of the DAC(s) driving the oscillator(s). Must be the same for
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all the outputs. */
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#define DAC_BITS 16
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/* Number of samples in a single ptracker averaging bin */
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#define PTRACKER_AVERAGE_SAMPLES 512
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/* 1.0 / (Speed of the phase shifter) - the higher value, the slower phase shifting.
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Used to prevent de-locking PLLs when shifting large offsets. */
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#define PHASE_SHIFTER_SPEED 1
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