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124 lines
4.9 KiB
C
124 lines
4.9 KiB
C
/*
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* This work is part of the White Rabbit project
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*
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* Copyright (C) 2010 - 2013 CERN (www.cern.ch)
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* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* Released according to the GNU GPL, version 2 or any later version.
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*/
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/* softpll_ng.h: public SoftPLL API header */
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#ifndef __SOFTPLL_NG_H
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#define __SOFTPLL_NG_H
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#include <stdint.h>
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/* SoftPLL operating modes, for mode parameter of spll_init(). */
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/* Grand Master - lock to 10 MHz external reference */
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#define SPLL_MODE_GRAND_MASTER 1
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/* Free running master - 125 MHz refrence free running, DDMTD locked to it */
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#define SPLL_MODE_FREE_RUNNING_MASTER 2
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/* Slave mode - 125 MHz reference locked to one of the input clocks */
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#define SPLL_MODE_SLAVE 3
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/* Disabled mode: SoftPLL inactive */
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#define SPLL_MODE_DISABLED 4
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/* Shortcut for 'channels' parameter in various API functions to perform operation on all channels */
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#define SPLL_ALL_CHANNELS 0xffffffff
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/* Aux clock flags */
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#define SPLL_AUX_ENABLED (1<<0) /* Locking the particular aux channel to the WR reference is enabled */
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#define SPLL_AUX_LOCKED (1<<1) /* The particular aux clock is already locked to WR reference */
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/* Phase detector types */
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#define SPLL_PD_DDMTD 0
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#define SPLL_PD_BANGBANG 1
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/* Note on channel naming:
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- ref_channel means a PHY recovered clock input. There can be one (as in WR core) or more (WR switch).
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- out_channel means an output channel, which represents PLL feedback signal from a local, tunable oscillator. Every SPLL implementation
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has at least one output channel, connected to the 125 / 62.5 MHz transceiver (WR) reference. This channel has always
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index 0 and is compared against all reference channels by the phase tracking mechanism.
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*/
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/* PUBLIC API */
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/*
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Initializes the SoftPLL to work in mode (mode). Extra parameters depend on choice of the mode:
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- for SPLL_MODE_GRAND_MASTER: non-zero (align_pps) value enables realignment of the WR reference rising edge to the
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rising edge of 10 MHz external clock that comes immediately after a PPS pulse
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- for SPLL_MODE_SLAVE: (ref_channel) indicates the reference channel to which we are locking our PLL.
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*/
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void spll_init(int mode, int ref_channel, int align_pps);
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/* Disables the SoftPLL and cleans up stuff */
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void spll_shutdown();
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/* Returns number of reference and output channels implemented in HW. */
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void spll_get_num_channels(int *n_ref, int *n_out);
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/* Starts locking output channel (out_channel) */
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void spll_start_channel(int out_channel);
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/* Stops locking output channel (out_channel) */
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void spll_stop_channel(int out_channel);
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/* Returns non-zero if output channel (out_channel) is locked to a WR reference */
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int spll_check_lock(int out_channel);
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/* Sets phase setpoint for given output channel. */
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void spll_set_phase_shift(int out_channel, int32_t value_picoseconds);
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/* Retreives the current phase shift and desired setpoint for given output channel */
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void spll_get_phase_shift(int out_channel, int32_t *current, int32_t *target);
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/* Returns non-zero if the given output channel is busy phase shifting to a new preset */
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int spll_shifter_busy(int out_channel);
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/* Returns phase detector type used by particular output channel. There are two phase detectors available:
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- DDMTD: locks only 62.5 / 125 MHz. Provides independent phase shift control for each output.
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- Bang-Bang: locks to any frequency that is a result of rational (M/N) multiplication of the reference frequency.
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The frequency can be set by spll_set_aux_frequency(). BB detector follows phase setpoint of channel 0 (WR reference),
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there is no per-output shift control.
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*/
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int spll_get_phase_detector_type(int out_channel);
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/* Sets the aux clock freuency when a BB detector is in use.
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Must be called prior to spll_start_channel(). If the frequency is out of available range,
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returns negative value */
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int spll_set_aux_frequency(int out_channel, int32_t frequency);
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/* Enables/disables phase tracking on channel (ref_channel). Phase is always measured between
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the WR local reference (out_channel 0) and ref_channel */
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void spll_enable_ptracker(int ref_channel, int enable);
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/* Reads tracked phase shift value for given reference channel */
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int spll_read_ptracker(int ref_channel, int32_t *phase_ps, int *enabled);
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/* Calls aux clock handling state machine. Must be called regularly (although it is not time-critical)
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in the main loop of the program if aux clocks are used in the design. */
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int spll_update_aux_clocks();
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/* Returns the status of given aux clock output (SPLL_AUX_) */
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int spll_get_aux_status(int out_channel);
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/* Debug/testing functions */
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/* Returns how many time the PLL has de-locked since last call of spll_init() */
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int spll_get_delock_count();
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/* Sets VCXO tuning DAC corresponding to output (out_channel) to a given value */
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void spll_set_dac(int out_channel, int value);
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/* Returns current DAC sample value for output (out_channel) */
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int spll_get_dac(int out_channel);
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#endif // __SOFTPLL_NG_H
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