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83 lines
3.1 KiB
C
83 lines
3.1 KiB
C
/*
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* This work is part of the White Rabbit project
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*
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* Copyright (C) 2010 - 2013 CERN (www.cern.ch)
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* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* Released according to the GNU GPL, version 2 or any later version.
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*/
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/* spll_external.h - definitions & prototypes for the
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external (10 MHz - Grandmaster mode) reference channel */
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#ifndef __SPLL_EXTERNAL_H
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#define __SPLL_EXTERNAL_H
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#include "spll_common.h"
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/* Alignment FSM states */
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/* 1st alignment stage, done before starting the ext channel PLL:
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alignment of the rising edge of the external clock (10 MHz), with
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the rising edge of the local reference (62.5/125 MHz) and the PPS
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signal. Because of non-integer ratio (6.25 or 12.5), the PLL must
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know which edges shall be kept at phase==0. We align to the edge of
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the 10 MHz clock which comes right after the edge of the PPS pulse
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(see drawing below):
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PLL reference (62.5 MHz) ____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|
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External clock (10 MHz) ^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|___
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External PPS ___________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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*/
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#define REALIGN_STAGE1 1
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#define REALIGN_STAGE1_WAIT 2
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/* 2nd alignment stage, done after the ext channel PLL has locked. We
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make sure that the switch's internal PPS signal is produced exactly
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on the edge of PLL reference in-phase with 10 MHz clock edge, which
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has come right after the PPS input
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PLL reference (62.5 MHz) ____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|
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External clock (10 MHz) ^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|___
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External PPS ___________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Internal PPS __________________________________|^^^^^^^^^|______________________________________________________________________
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^ aligned clock edges and PPS
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*/
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#define REALIGN_STAGE2 3
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#define REALIGN_STAGE2_WAIT 4
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/* Error state - PPS signal missing or of bad frequency */
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#define REALIGN_PPS_INVALID 5
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/* Realignment is disabled (i.e. the switch inputs only the reference
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* frequency, but not time) */
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#define REALIGN_DISABLED 6
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/* Realignment done */
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#define REALIGN_DONE 7
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struct spll_external_state {
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int ref_src;
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int sample_n;
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int ph_err_offset, ph_err_cur, ph_err_d0, ph_raw_d0;
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int realign_clocks;
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int realign_state;
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int realign_timer;
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spll_pi_t pi;
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spll_lowpass_t lp_short, lp_long;
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spll_lock_det_t ld;
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};
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void external_init(volatile struct spll_external_state *s, int ext_ref,
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int realign_clocks);
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int external_update(struct spll_external_state *s, int tag, int source);
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void external_start(struct spll_external_state *s);
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int external_locked(struct spll_external_state *s);
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#endif // __SPLL_EXTERNAL_H
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