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55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/*
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* This work is part of the White Rabbit project
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*
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* Copyright (C) 2010 - 2013 CERN (www.cern.ch)
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* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* Released according to the GNU GPL, version 2 or any later version.
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*/
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/* spll_main.h - the main DDMTD PLL. Locks output clock to any reference
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with programmable phase shift. */
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#ifndef __SPLL_MAIN_H
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#define __SPLL_MAIN_H
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#include "spll_common.h"
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/* State of the Main PLL */
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struct spll_main_state {
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int state;
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spll_pi_t pi;
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spll_lock_det_t ld;
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int adder_ref, adder_out, tag_ref, tag_out, tag_ref_d, tag_out_d;
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// tag sequencing stuff
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uint32_t seq_ref, seq_out;
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int match_state;
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int match_seq;
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int phase_shift_target;
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int phase_shift_current;
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int id_ref, id_out; /* IDs of the reference and the output channel */
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int sample_n;
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int delock_count;
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int dac_index;
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};
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void mpll_init(struct spll_main_state *s, int id_ref,
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int id_out);
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void mpll_stop(struct spll_main_state *s);
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void mpll_start(struct spll_main_state *s);
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int mpll_update(struct spll_main_state *s, int tag, int source);
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int mpll_set_phase_shift(struct spll_main_state *s,
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int desired_shift);
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int mpll_shifter_busy(struct spll_main_state *s);
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#endif // __SPLL_MAIN_H
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