45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
(ExpressProject "empty_design"
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(ProjectVersion "19981106")
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(SoftwareVersion "24.1 S004 (4290201) [4/17/2025]-[07/30/25]")
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(ProjectType "PCB")
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(Folder "Design Resources"
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(Folder "Library")
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("Allegro Netlist Directory" "allegro")
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(DOCKED "TRUE")
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(DOCKING_POSITION "59420")
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(NoModify)
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(File ".\empty_design.dsn"
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(Type "Schematic Design"))
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(BuildFileAddedOrDeleted "x")
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(CompileFileAddedOrDeleted "x")
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("Allegro Netlist Output Board File" ".\empty_design.brd"))
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(Folder "Layout"
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(File ".\empty_design.brd"
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(Type "Board File")
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(OutputBoard ".\empty_design.brd")
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(NetListPath ".\allegro")
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(ActiveBoard "1")))
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(Folder "Outputs")
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(Folder "Referenced Projects")
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(Folder "PSpice Resources"
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(Folder "Simulation Profiles")
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(Folder "Model Libraries"
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(Sort User))
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(Folder "Stimulus Files"
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(Sort User))
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(Folder "Include Files"
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(Sort User)))
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(Folder "Logs")
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(MPSSessionName "gman")
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(PartMRUSelector)
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(GlobalState
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(FileView
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(Path "Design Resources")
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(Path "Layout"))
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(HierarchyView)
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(Doc
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(Type "COrCapturePMDoc")
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(Frame
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(Placement "44 0 1 -1 -1 -1 -1 0 200 0 684"))
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(Tab 0))))
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