uob-hep-pc072/hardware/Cadence/top/archive_libs/cndiscrete/cndiode/entity/verilog.v

// generated by newgenasym  Tue Aug 19 15:43:19 2014


module diode (a, k);
    parameter    size = 1;
    inout [size-1:0] a;
    inout [size-1:0] k;


    initial
        begin
        end

endmodule