13 lines
343 B
VHDL

-- generated by newgenasym Mon May 21 10:35:03 2012
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \usblc6-2\ is
port (
GND: IN STD_LOGIC;
\i/o1\: INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
\i/o2\: INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
VBUS: IN STD_LOGIC);
end \usblc6-2\;