forked from AllSpiceMirrors/uob-hep-pc072
18 lines
244 B
Verilog
18 lines
244 B
Verilog
// generated by newgenasym Thu Jun 18 16:06:36 2015
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module \74avc1t45 (a, b, dir, gnd, vcca, vccb);
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output a;
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input b;
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input dir;
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input gnd;
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input vcca;
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input vccb;
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initial
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begin
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end
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endmodule
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