forked from AllSpiceMirrors/uob-hep-pc072
15 lines
373 B
VHDL
15 lines
373 B
VHDL
-- generated by newgenasym Thu Jun 18 16:06:36 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74avc1t45\ is
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port (
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A: OUT STD_LOGIC;
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B: IN STD_LOGIC;
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DIR: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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VCCA: IN STD_LOGIC;
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VCCB: IN STD_LOGIC);
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end \74avc1t45\;
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