forked from AllSpiceMirrors/uob-hep-pc072
15 lines
208 B
Verilog
15 lines
208 B
Verilog
// generated by newgenasym Thu Sep 18 11:56:59 2003
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module \74lvc07a (a, y);
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parameter size = 1;
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input [size-1:0] a;
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output [size-1:0] y;
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initial
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begin
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end
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endmodule
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