14 lines
340 B
VHDL

-- generated by newgenasym Thu Sep 18 11:56:59 2003
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \74lvc07a\ is
generic (
size:positive:= 1
);
port (
A: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end \74lvc07a\;