14 lines
329 B
VHDL

-- generated by newgenasym Tue Jan 28 10:01:11 2025
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity LD3985 is
port (
BYPASS: INOUT STD_LOGIC;
GND: IN STD_LOGIC;
VI: IN STD_LOGIC;
VINH: INOUT STD_LOGIC;
VO: IN STD_LOGIC);
end LD3985;