forked from AllSpiceMirrors/uob-hep-pc072
15 lines
220 B
Verilog
15 lines
220 B
Verilog
// generated by newgenasym Thu Jul 3 10:38:38 2003
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module header2x1 (a, b);
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parameter size = 1;
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inout [size-1:0] a;
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inout [size-1:0] b;
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initial
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begin
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end
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endmodule
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