forked from AllSpiceMirrors/uob-hep-pc072
16 lines
251 B
Verilog
16 lines
251 B
Verilog
// generated by newgenasym Thu Jul 3 10:38:57 2003
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module kkcon3 (a1, a2, b1);
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parameter size = 1;
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inout [size-1:0] a1;
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inout [size-1:0] a2;
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inout [size-1:0] b1;
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initial
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begin
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end
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endmodule
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