forked from AllSpiceMirrors/uob-hep-pc072
14 lines
167 B
Verilog
14 lines
167 B
Verilog
// generated by newgenasym Fri Jun 21 11:27:11 2024
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module ss16fp (a, c);
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inout a;
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inout c;
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initial
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begin
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end
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endmodule
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