David Cussans 282b644640 Added LEDs to front_panel_jtag_serial design. Exported to PCB

2025-02-13 13:36:51 +00:00

..

bom

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2025-02-10 15:19:29 +00:00

cfg_package

REplaced 470uF case-E caps (C17,C44,C77,C80) with lower profile 220uF

2023-04-17 16:10:51 +01:00

cfg_pic

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2025-02-10 15:19:29 +00:00

cfg_verilog

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2025-02-10 15:19:29 +00:00

cfg_vhdl

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2025-02-10 15:19:29 +00:00

images

Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly

2025-01-23 13:19:18 +00:00

packaged

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2025-02-10 15:19:29 +00:00

physical

Added LEDs to front_panel_jtag_serial design. Exported to PCB

2025-02-13 13:36:51 +00:00

sch_1

Pushing files flagged as changed by GIT

2025-02-10 15:19:29 +00:00