David Cussans 21e21230ec Fixed the following schematic bugs ...

* Signals into D-FF U8,U3,U2 all had the same net names ( DFF_CLK_P<0>
  etc. ) would have wired all inputs together. Very wrong
* One of biasing resistors for D-FF input wasn't connected.
* Diff pairs into FPGA connector inverted ( P<--> N ) AUXIO_7 pair ,
  DATA_FROM_UPSTREAM_<1> pair, TIMING.UPSTREAM_DATA_<2> pair. Pointed
  out by Pete Hastings

* To Do: Clock to FPGA from clock generator not connected. ( Whoops !)

2023-03-17 10:39:03 +00:00

1.2 MiB

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