104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/*
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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* Copyright 2013 Benjamin Vernoux <bvernoux@gmail.com>
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*
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* This file is part of AirSpy (based on HackRF project).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include <stdint.h>
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#include "fault_handler.h"
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typedef struct
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{
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr; /* Link Register. */
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uint32_t pc; /* Program Counter. */
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uint32_t psr;/* Program Status Register. */
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} hard_fault_stack_t;
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/* Code Compatible with CortexM0, M3, M4 (R4 & R5 are modified for ARCH 6M) */
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__attribute__((naked))
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void hard_fault_handler(void)
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{
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#if defined(__ARM_ARCH_6M__)
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__asm__("MOVS R4, #4");
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__asm__("MOV R5, LR");
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__asm__("TST R4, R5");
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__asm__("BEQ _MSP");
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__asm__("MRS R0, PSP");
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__asm__("B hard_fault_handler_c");
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__asm__("_MSP:");
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__asm__("MRS R0, MSP");
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__asm__("B hard_fault_handler_c");
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#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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__asm__("TST LR, #4");
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__asm__("ITE EQ");
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__asm__("MRSEQ R0, MSP");
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__asm__("MRSNE R0, PSP");
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__asm__("B hard_fault_handler_c");
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#else
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#error "unsupported CortexMx architecture"
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#endif
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}
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volatile hard_fault_stack_t* hard_fault_stack_pt;
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__attribute__((used)) void hard_fault_handler_c(uint32_t* args)
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{
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/* hard_fault_stack_pt contains registers saved before the hard fault */
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hard_fault_stack_pt = (hard_fault_stack_t*)args;
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/*
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// args[0-7]: r0, r1, r2, r3, r12, lr, pc, psr
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// Other interesting registers to examine (see SCB data structure):
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// CFSR: Configurable Fault Status Register
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// HFSR: Hard Fault Status Register
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// DFSR: Debug Fault Status Register
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// AFSR: Auxiliary Fault Status Register
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// MMAR: MemManage Fault Address Register
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// BFAR: Bus Fault Address Register
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if( SCB->HFSR & SCB_HFSR_FORCED ) {
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if( SCB->CFSR & SCB_CFSR_BFSR_BFARVALID ) {
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SCB->BFAR;
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if( SCB->CFSR & CSCB_CFSR_BFSR_PRECISERR ) {
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}
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}
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}
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*/
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__asm("BKPT #0\n") ; // Break into the debugger
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while(1);
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}
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void mem_manage_handler() {
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while(1);
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}
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void bus_fault_handler() {
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while(1);
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}
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void usage_fault_handler() {
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while(1);
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}
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