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This keeps the i2s_dma_buf as a 128-byte ring buffer, but instead of
being organized as 32 words of 32 bits each, it introduces the notion of a
typedef struct {
s32 left, right;
} raw_sample_t;
and makes the DMA ring-buffer be 16 of these entries instead.
The USB output buffer has also been changed to match this sample model,
and renamed to better reflect the fact that it's for USB.
The i2s PIO program is changed to use auto-pull to make it a bit more
streamlined. It could also have kept doing the explicit 'pull'
instructions, but that would have required another non-looping cycle to
set up.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
110 lines
2.8 KiB
Plaintext
110 lines
2.8 KiB
Plaintext
;
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; We want a target sample frequency of 48kHz, which
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; with 32-bit i2s data means a dot clock of 3.072MHz.
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;
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; We clock the rp2354 to 153.6MHz, which is exactly
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; 50x that dot clock frequency.
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;
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; We then use a PIO divider of 25, and make the PIO
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; program do 2 cycles per clock.
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;
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; i2s: FSYNC and each data bit is transmitted on the
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; falling edge of BCLK, so we set those bits the cycle
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; when BCLK goes low ("side 0") so that they are stable
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; on the rising edge ("side 1").
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;
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; The actual data is transmitted one cycle after FSYNC
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; goes low
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;
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.pio_version 1
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.program i2s_tx
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.fifo tx
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.clock_div 25
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.side_set 2
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.wrap_target
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out pins, 1 side 0b00 ; Cycle 0: FSYNC low. Output R0 (from previous frame)
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public start_tx:
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set x, 30 side 0b01
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loop_low:
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out pins, 1 side 0b00 ; Cycle 2: Output L31..L1
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jmp x-- loop_low side 0b01
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out pins, 1 side 0b10 ; Cycle 64: FSYNC high. Output L0
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set x, 30 side 0b11
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loop_high:
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out pins, 1 side 0b10 ; Cycle 66: Output R31..R1
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jmp x-- loop_high side 0b11
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.wrap
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% c-sdk {
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//
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// 'pin' is BCLK (MCU output)
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// 'pin+1' is FSYNC (MCU output)
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// 'pin+2' is DIN (MCU output! It's DIN from the CODEC standpoint!)
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// 'pin+3' is DOUT (MCU input! It's DOUT from the CODEC standpoint!)
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//
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static inline void i2s_tx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_tx_program_get_default_config(offset);
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pio_gpio_init(pio, pin);
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pio_gpio_init(pio, pin+1);
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pio_gpio_init(pio, pin+2);
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pio_gpio_init(pio, pin+3);
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// three output pins, one input
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pio_sm_set_pindirs_with_mask(pio, sm, 0b0111 << pin, 0b1111 << pin);
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// BCLK and FSYNC using sideset
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sm_config_set_sideset_pin_base(&c, pin);
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// DOUT using 'OUT' instruction
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sm_config_set_out_pins(&c, pin+2, 1);
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// Auto-pull, shift left (MSB first), 32 bits
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sm_config_set_out_shift(&c, false, true, 32);
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// Load and run the program
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pio_sm_init(pio, sm, offset + i2s_tx_offset_start_tx, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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.program i2s_rx
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.fifo rx
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.clock_div 25
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public start_rx:
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wait 1 jmppin ; wait for FSYNC going high
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wait 0 jmppin [1] ; wait for FSYNC going low, delay to sample middle
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.wrap_target
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set x, 30
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loop_left:
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in pins, 1
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jmp x-- loop_left
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in pins, 1 ; sample LSB of left channel
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set x, 30
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loop_right:
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in pins, 1
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jmp x-- loop_right
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in pins, 1 ; sample LSB of right channel
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.wrap
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% c-sdk {
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static inline void i2s_rx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_rx_program_get_default_config(offset);
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sm_config_set_jmp_pin(&c, pin+1); // FSYNC
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sm_config_set_in_pins(&c, pin+3); // DOUT
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// Auto-push, shift left (MSB first), 32 bits
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sm_config_set_in_shift(&c, false, true, 32);
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// Load and run the program
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pio_sm_init(pio, sm, offset + i2s_rx_offset_start_rx, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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