add epaper connector caps + netlabels

This commit is contained in:
AllSpiceUser 2023-11-01 00:58:18 -05:00
parent 4070e9ad29
commit 8f2b17e3f6
3 changed files with 17 additions and 0 deletions

17
PCB_Project.PrjPcb generated
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@ -131,6 +131,23 @@ ClassGenCCAutoRoomEnabled=0
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=HRCKAVRY
[Document6]
DocumentPath=components\Capacitor.SchLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=0
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Configuration1]

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LOADING design file

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12341234ABCDABCDTitleSizeANumberRevisionDate=CurrentDateFileepaper.SchDocSheetofDrawn By:V_PAPERSPI_MOPage_turner_top[3B]SPI_SCKPage_turner_top[3B]SPI_CSPage_turner_top[3B]GND_PAPERPage_turner_top[3C]Component queueConnector, E-Ink Molex PFC24/0.5MM123456789101112131415161718192021222324M2M1J?D/CPage_turner_top[3B]RSTPage_turner_top[3B]BUSYPage_turner_top[3B]V_PAPER_INT1μFC?0.1μFC?1μFC?1μFC?1μFC?1μFC?1μFC?1μFC?GNDGDRRESE1μFC?1μFC?GNDBSBUSYRESETD/CSPI_CSSPI_SKSPI_MO3V3GNDPREVGHPREVGL
LOADING design file