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[schematic] Add testpoints for all communication / power signals #23

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opened 2023-11-03 14:51:05 +00:00 by AllSpiceAlice · 0 comments
AllSpiceAlice commented 2023-11-03 14:51:05 +00:00
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SPI bus (Clk, mo, cs)
D/C
RST
Busy
GND
VBAT
ESP32 5V
ESP32 VBAT (not coincell, lipo)

SPI bus (Clk, mo, cs) D/C RST Busy GND VBAT ESP32 5V ESP32 VBAT (not coincell, lipo)
AllSpiceAlice added this to the Create proto sch/pcb milestone 2023-11-03 14:51:05 +00:00
AllSpiceAlice added the
dfm
 label 2023-11-03 14:51:05 +00:00
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dfm
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documentation
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eol
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feature
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firmware
Requires FW attention
layout
Requires PCB layout attention
mechanical
Requires ME attention
priority/1 - idea
Nice to have or idea to capture
priority/2 - low
Should be resolved eventually
priority/3 - medium
Should be resolved before product launch
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Should be resolved before next release
priority/5 - critical
Must be fixed immediately - blocking item
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Reference: AllSpice-Demos/AllSpice-epaper-demo#23
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