AllSpice-Demos/Altium-Demo
AllSpice-Demos/Altium-Demo
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Update generate-bom to 0.8 #60

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allspice-hermes wants to merge 1 commits from gautam-patch-1 into main
pull from: gautam-patch-1
merge into: AllSpice-Demos:main
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allspice-hermes commented 2025-06-10 16:55:19 +00:00
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This short description prepends any pull request. It is fully markdown compatible. See markdown guide for examples of what you can do!

Resolved Issues

...

Description

...

Design Review Checklist

Process
  • Commits in correct branch
  • Schematic and PCB file names follow standard
  • Export necessary review files (3D model, BOM, etc.)
  • Update relevant system architecture documents
  • Update project README page
  • Simulations uploaded and outputs explained
System
  • Power
    • Sufficient power supplied from upstream source
    • Supply rated for necessary country specifications
    • Estimated total worst-case power supply draw
  • Connectors
    • I/Os are specified
    • Sufficient Current and Voltage rating
    • Mating connectors have matching pinout
    • Same contact material specified for mating connectors
  • Testing
    • Test procedure written
  • Environmental
    • Specified min/max operating temperature
    • Specified min/max storage temperature
    • Specified min/max humidity
  • ROHS compliance requirement review
Components
  • Unpopulated components are denoted DNI
  • Components meet environmental specifications
  • All components have quantity, reference designator and description
  • Suggested and alternate manufacturers listed
  • Price and stock checked for each component
  • Component derating
    • Voltage
    • Current
    • Power at worst-case operating temperature
    • Temperature at worst-case power
Schematics
  • Document
    • Dot on each connection
    • No four-point connections
    • Title block completed for each sheet
    • All components have reference designators and values
    • Multi-part components don't have unplaced symbols
    • Page title present and consistent on all pages if not in title block
    • Symbols identify open collector/drain pins and internal pulled up/down pins
    • Pin names and attributes on symbols with multi-function pins match usage
    • Components follow preferred reference designator pattern
  • External I/O
    • Filtered for EMI
    • Protected against ESD
    • Unused inputs terminated
  • Microcontrollers / ICs
    • Predictable or controlled power-up state
      • Reset filtered
    • Sufficient bypass capacitance
    • Oscillators checked for reliable startup
    • Pullups on open-collector pins
    • Logic-low and logic-high voltage levels checked
    • No-connect pins labeled NC
    • Clock lines terminated
    • Check for power-off voltage & CMOS latchup
    • Review datasheet errata/apnotes
  • Busses
    • UART TX/RX pairs correct
    • I2C SDA/SCL pullups per TI guideline
    • Setup/hold/access times considered
  • Analog
    • Sufficient power rails
    • Amplifier stability
    • Rise/fall rate considerations
  • General
    • Bulk capacitance calculated
    • Polarized components checked
    • No reverse voltage on electrolytic/tantalum
    • Derating checked
    • Capacitance on LDOs
    • Comparator delays/slew rates
    • Opamp common-mode range
    • Custom part pin numbers verified
    • Transistor reverse current/voltage
    • Consistent power net naming
    • Debug features included
PCB
  • Manufacturing
    • Requirements on fab layer
      • Plating: material and thickness
      • Stack-up
      • Trace/space and hole size
      • Colors (PCB/silkscreen)
      • Controlled impedance
      • Blind/buried vias
      • Panelization and routing
      • Drill table
      • Specs exceed tolerances
    • Minimized power plane spacing
    • Proper solder paste
    • Fiducials if needed
  • Footprints
    • Pin 1 marked
    • Polarities: diodes, caps, connectors
    • Dimensions verified with datasheet
    • Thermal pads present
  • Placement
    • Jumpers & debug access
    • Proper resistor placements
    • Small SMPS loop paths
    • Caps near ICs/connectors
    • Drivers near connectors
    • SMT on top, THT on bottom
  • Clearance
    • Keep-outs honored
    • Trace/component spacing per voltage
    • Away from board edges
  • Mechanical
    • CAD file uploaded
    • Connector clearance
    • Harness bend radius
    • Isolated mounting holes
      • Via stitching present
    • Hole margin for plating
    • Board outline & enclosure defined
    • Milled corners
  • Electrical
    • All traces routed
    • Single-point analog/digital common
    • ERC passes
    • Isolation barriers
  • Signal integrity
    • Ground plane gaps minimized
    • High-speed signals over ground
    • Stub-free routing
    • Differential pair spacing
    • Transmission line termination
    • Short crystal traces
    • Crystal guard ring
    • No traces under sensitive/noisy parts
    • Via fencing (<1/20 λ)
    • Shielding can options
  • Copper pour
    • Planes poured
    • No high-impedance paths
    • No pour between adjacent IC pins
  • Traces
    • Sufficient angle to pad
    • Proper trace width & via sizing
    • Mitered bends or curves
  • Thermal
    • Heat-sensitive components placed properly
    • Thermal vias in pads
  • Testing
    • Test points added
    • Nearby ground connections
  • Silk screen
    • Notes: rev, date, serial space
    • No silk on pads/vias
    • Max 2 directions readable
    • Font legibility
    • Pinouts and fuse labels
    • Functional labeling
> *This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!* ## Resolved Issues <!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" --> ... ## Description <!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? --> ... ## Design Review Checklist <details> <summary>Process</summary> - [ ] Commits in correct branch - [ ] Schematic and PCB file names follow standard - [ ] Export necessary review files (3D model, BOM, etc.) - [ ] Update relevant system architecture documents - [ ] Update project README page - [ ] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [ ] Power - [ ] Sufficient power supplied from upstream source - [ ] Supply rated for necessary country specifications - [ ] Estimated total worst-case power supply draw - [ ] Connectors - [ ] I/Os are specified - [ ] Sufficient Current and Voltage rating - [ ] Mating connectors have matching pinout - [ ] Same contact material specified for mating connectors - [ ] Testing - [ ] Test procedure written - [ ] Environmental - [ ] Specified min/max operating temperature - [ ] Specified min/max storage temperature - [ ] Specified min/max humidity - [ ] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [ ] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [ ] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [ ] Voltage - [ ] Current - [ ] Power at worst-case operating temperature - [ ] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [ ] Document - [ ] Dot on each connection - [ ] No four-point connections - [ ] Title block completed for each sheet - [ ] All components have reference designators and values - [ ] Multi-part components don't have unplaced symbols - [ ] Page title present and consistent on all pages if not in title block - [ ] Symbols identify open collector/drain pins and internal pulled up/down pins - [ ] Pin names and attributes on symbols with multi-function pins match usage - [ ] Components follow preferred reference designator pattern - [ ] External I/O - [ ] Filtered for EMI - [ ] Protected against ESD - [ ] Unused inputs terminated - [ ] Microcontrollers / ICs - [ ] Predictable or controlled power-up state - [ ] Reset filtered - [ ] Sufficient bypass capacitance - [ ] Oscillators checked for reliable startup - [ ] Pullups on open-collector pins - [ ] Logic-low and logic-high voltage levels checked - [ ] No-connect pins labeled NC - [ ] Clock lines terminated - [ ] Check for power-off voltage & CMOS latchup - [ ] Review datasheet errata/apnotes - [ ] Busses - [ ] UART TX/RX pairs correct - [ ] I2C SDA/SCL pullups per [TI guideline](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Setup/hold/access times considered - [ ] Analog - [ ] Sufficient power rails - [ ] Amplifier stability - [ ] Rise/fall rate considerations - [ ] General - [ ] Bulk capacitance calculated - [ ] Polarized components checked - [ ] No reverse voltage on electrolytic/tantalum - [ ] Derating checked - [ ] Capacitance on LDOs - [ ] Comparator delays/slew rates - [ ] Opamp common-mode range - [ ] Custom part pin numbers verified - [ ] Transistor reverse current/voltage - [ ] Consistent power net naming - [ ] Debug features included </details> <details> <summary>PCB</summary> - [ ] Manufacturing - [ ] Requirements on `fab` layer - [ ] Plating: material and thickness - [ ] Stack-up - [ ] Trace/space and hole size - [ ] Colors (PCB/silkscreen) - [ ] Controlled impedance - [ ] Blind/buried vias - [ ] Panelization and routing - [ ] Drill table - [ ] Specs exceed tolerances - [ ] Minimized power plane spacing - [ ] Proper solder paste - [ ] Fiducials if needed - [ ] Footprints - [ ] Pin 1 marked - [ ] Polarities: diodes, caps, connectors - [ ] Dimensions verified with datasheet - [ ] Thermal pads present - [ ] Placement - [ ] Jumpers & debug access - [ ] Proper resistor placements - [ ] Small SMPS loop paths - [ ] Caps near ICs/connectors - [ ] Drivers near connectors - [ ] SMT on top, THT on bottom - [ ] Clearance - [ ] Keep-outs honored - [ ] Trace/component spacing per voltage - [ ] Away from board edges - [ ] Mechanical - [ ] CAD file uploaded - [ ] Connector clearance - [ ] Harness bend radius - [ ] Isolated mounting holes - [ ] Via stitching present - [ ] Hole margin for plating - [ ] Board outline & enclosure defined - [ ] Milled corners - [ ] Electrical - [ ] All traces routed - [ ] Single-point analog/digital common - [ ] ERC passes - [ ] Isolation barriers - [ ] Signal integrity - [ ] Ground plane gaps minimized - [ ] High-speed signals over ground - [ ] Stub-free routing - [ ] Differential pair spacing - [ ] Transmission line termination - [ ] Short crystal traces - [ ] Crystal guard ring - [ ] No traces under sensitive/noisy parts - [ ] Via fencing (<1/20 λ) - [ ] Shielding can options - [ ] Copper pour - [ ] Planes poured - [ ] No high-impedance paths - [ ] No pour between adjacent IC pins - [ ] Traces - [ ] Sufficient angle to pad - [ ] Proper trace width & via sizing - [ ] Mitered bends or curves - [ ] Thermal - [ ] Heat-sensitive components placed properly - [ ] Thermal vias in pads - [ ] Testing - [ ] Test points added - [ ] Nearby ground connections - [ ] Silk screen - [ ] Notes: rev, date, serial space - [ ] No silk on pads/vias - [ ] Max 2 directions readable - [ ] Font legibility - [ ] Pinouts and fuse labels - [ ] Functional labeling </details> <!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ -->
allspice-hermes added 1 commit 2025-06-10 16:55:19 +00:00
Update generate-bom to 0.8
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43f519191e
john-allspice commented 2026-03-18 14:55:06 +00:00
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@allspice-hermes any objection to merging this branch and closing this DR? I want to use this for the example-repos and it would be good to have only 1 open DR that's more relevant?

@allspice-hermes any objection to merging this branch and closing this DR? I want to use this for the example-repos and it would be good to have only 1 open DR that's more relevant?
All checks were successful
Python-py-allspice / py-allspice test (push) Successful in 29s
Details
Generate BOM / Generate_BOM (push) Successful in 2m8s
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bug
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dfm
Design for manufacturing consideration
documentation
Improvements to supporting documentation
eol
End of life component
feature
New feature or request
firmware
Requires FW attention
layout
Requires PCB layout attention
mechanical
Requires ME attention
priority/1 - idea
Nice to have or idea to capture
priority/2 - low
Should be resolved eventually
priority/3 - medium
Should be resolved before product launch
priority/4 - high
Should be resolved before next release
priority/5 - critical
Must be fixed immediately - blocking item
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Reference: AllSpice-Demos/Altium-Demo#60
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