141 lines
5.5 KiB
Markdown
141 lines
5.5 KiB
Markdown
---
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name: "AllSpice component review template"
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about: "Optional description"
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---
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*This short description prepends any pull request. It is fully markdown compatible. See [markdown guide](https://www.markdownguide.org/cheat-sheet/) for examples of what you can do!*
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## Resolved Issues
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<!-- Include any relevant issues closed by this pull request. Use the form "Closes #<number of issue>" -->
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...
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## Description
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<!-- Include a description for this design review. What is the primary purpose? What will be the status of this design after approval? -->
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...
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## Design Review Checklist
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### Process
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- [ ] Commits in correct branch
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- [ ] File names follow standard
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- [ ] Update project README page
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### System
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- [ ] Power
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- [ ] Supply rated for necessary country specifications
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- [ ] Estimated total worst-case power supply draw
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- [ ] Connectors
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- [ ] Sufficient Current and Voltage rating
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- [ ] Mating connectors have matching pinout
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- [ ] Same contact material specified for mating connectors
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- [ ] Testing
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- [ ] Test procedure written
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- [ ] Environmental
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- [ ] Specified min/max operating temperature
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- [ ] Specified min/max storage temperature
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- [ ] Specified min/max humidity
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- [ ] ROHS compliance requirement review
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### Components
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- [ ] Components meet environmental specifications
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- [ ] All components have quantity, reference designator and description
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- [ ] Suggested and alternate manufacturers listed
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- [ ] Price and stock checked for each component
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- [ ] Component derating
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- [ ] Voltage
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- [ ] Current
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- [ ] Power at worst-case operating temperature
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- [ ] Temperature at worst-case power
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### Schematics
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- [ ] Microcontrollers / ICs
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- [ ] Check the data sheet errata and apnotes for weird IC behaviors
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- [ ] Busses
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- [ ] UART/USART TX->RX and RX<-TX
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- [ ] I2C SDA and SCL pins correct(https://www.ti.com/lit/an/slva689/slva689.pdf)
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- [ ] Analog
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- [ ] Sufficient power rails for analog circuits
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- [ ] Amplifiers checked for stability
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- [ ] Consider signal rate-of-rise and fall for noise radiation
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- [ ] General
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- [ ] Sufficient bulk capacitance calculated
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- [ ] Polarized components checked
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- [ ] Electrolytic/tantalum capacitors checked for no reverse voltage
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- [ ] Electrolytic/tantalum capacitors temperature/voltage derating sufficient for MTBF
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- [ ] Check pin numbers of all custom-generated parts
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- [ ] Check reverse base-emitter current/voltage on bipolar transistors
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- [ ] Power nets use preferred and consistent naming (ex. no `3.3V` vs `+3.3V`)
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- [ ] Debug resources added by design (leds, serial ports, etc.) even if unpopulated by default
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### PCB
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- [ ] Manufacturing
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- [ ] PCB manufacturing requirements noted on `fab` layer
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- [ ] Plating specified
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- [ ] Plating material
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- [ ] Plating thickness
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- [ ] Layer stack-up specified
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- [ ] Minimum trace/space specified
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- [ ] Minimum hole size specified
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- [ ] Controlled impedance specified
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- [ ] Blind or buried vias specified
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- [ ] Footprints
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- [ ] Pin 1 marked in a consistent manner
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- [ ] Component polarity marked
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- [ ] Diodes, LEDs
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- [ ] Electrolytic, tantalum capacitors
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- [ ] Keyed components like connectors
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- [ ] Footprint dimensions cross-checked with datasheet recommendation
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- [ ] Sufficient thermal pads on high-power components or nets
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- [ ] Clearance
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- [ ] Keep-out areas honored
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- [ ] Around mounting holes
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- [ ] For programming tools
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- [ ] For assembly tools (wrenches, screwdrivers etc.)
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- [ ] For connectors
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- [ ] Trace-to-trace clearance based upon voltage rating
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- [ ] Component size based upon voltage rating
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- [ ] Mechanical
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- [ ] CAD file uploaded
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- [ ] Clearance above connectors
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- [ ] Clearance below through-hole components
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- [ ] Mounting holes electrically isolated if necessary
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- [ ] Mounting holes have via stitching
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- [ ] Hole diameters leave margin for plating
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- [ ] Electrical
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- [ ] ERC passes
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- [ ] Isolation barriers are large enough
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- [ ] Signal integrity
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- [ ] Gaps in ground planes checked and minimized
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- [ ] High-speed signals avoid gaps in ground planes
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- [ ] Stubs minimized for high-speed signals
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- [ ] Differential pair spacing based upon impedance matching
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- [ ] Via fencing of sensitive RF transission lines done with the proper via spacing (< 1/20 lambda)
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- [ ] Option for a shielding can over sensitive circuitry e.g. RF?
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- [ ] Copper pour
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- [ ] All planes have been poured
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- [ ] Planes and pours checked for high-impedance paths
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- [ ] No pour between adjacent pins on ICs
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- [ ] Traces
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- [ ] Trace-pad connections sufficiently obtuse (angle 90 deg or more)
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- [ ] Trace widths sufficient for the current draw and max heating
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- [ ] No connections between adjacent pins on ICs
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- [ ] Vias for internal power traces sufficiently large
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- [ ] Mitered bends or soft curves (r > 3 trace width) for impedance sensitive traces
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- [ ] Thermal
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- [ ] Temperature sensitive components placed away from hot components
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- [ ] Thermal vias in thermal pads
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- [ ] Silk screen
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- [ ] Notes and documentation
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- [ ] Updated revision number
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- [ ] Updated date
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- [ ] No silk screen over pads / vias
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- [ ] Text is readable from at most two directions
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- [ ] Silk screen size / font will legible after printing
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- [ ] Connector pin-outs labeled
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- [ ] Fuse size and type marked on PCB
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- [ ] Functional groups marked
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- [ ] Functionality labeled
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- [ ] Test points
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- [ ] LEDs
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- [ ] Buttons
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- [ ] Connectors/terminals
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- [ ] Jumpers/fuses
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<!-- Special thanks to Henrik Enggaard Hansen for https://pcbchecklist.com/ --> |