AllSpice-Demos/Archimajor-DRCY-Demo

Fork 0

Prototype-to-Pilot DFM Changes #2

Closed

allspice-carah wants to merge 2 commits from develop into main

allspice-carah commented

2026-03-17 17:06:47 +00:00

Owner

Description

V0.4 Fixes design errors from V0.3

Design Review Checklist

Process

Commits in correct branch
Schematic and PCB file names follow standard
Export necessary review files (3D model, BOM, etc.)
Update relevant system architecture documents
Update project README page
Simulations uploaded and outputs explained

System

Power
- Sufficient power supplied from upstream source
- Supply rated for necessary country specifications
- Estimated total worst-case power supply draw
Connectors
- I/Os are specified
- Sufficient Current and Voltage rating
- Mating connectors have matching pinout
- Same contact material specified for mating connectors
Testing
- Test procedure written
Environmental
- Specified min/max operating temperature
- Specified min/max storage temperature
- Specified min/max humidity
ROHS compliance requirement review

Components

Unpopulated components are denoted DNI
Components meet environmental specifications
All components have quantity, reference designator and description
Suggested and alternate manufacturers listed
Price and stock checked for each component
Component derating
- Voltage
- Current
- Power at worst-case operating temperature
- Temperature at worst-case power

Schematics

Document
- Dot on each connection
- No four-point connections
- Title block completed for each sheet
- All components have reference designators and values
- Multi-part components don't have unplaced symbols
- Page title present and consistent on all pages if not in title block
- Symbols identify open collector/drain pins and internal pulled up/down pins
- Pin names and attributes match design usage
- Reference designators follow standard
External I/O
- EMI filtered
- ESD protection
- Unused inputs terminated
Microcontrollers / ICs
- Controlled power-up state
  - Reset filtered
- Bypass caps
- Oscillator startup
- Pullups on OC pins
- Logic levels verified
- No-connect pins labeled
- Termination for clock lines
- Input voltage risks & latchup
- Datasheet errata reviewed
Busses
- UART TX->RX and RX<-TX
- I2C pullups per capacitance
- Timing reviewed
Analog
- Rail availability
- Amp stability
- Rise/fall timing
General
- Bulk capacitance
- Polarized components
- Reverse voltage checked
- Derating for MTBF
- LDOs have sufficient caps
- Comparator timing
- Opamp input range
- Custom pin numbers verified
- BJT reverse current
- Net naming consistent
- Debug resources added

PCB

Manufacturing
- fab layer info present
  - Plating
  - Stack-up
  - Trace/space
  - Hole size
  - PCB/silkscreen color
  - Impedance
  - Blind/buried vias
  - Panelization and routing
  - Drill table
  - Tolerance margins
- Power planes spaced
- Solder paste OK
- Fiducials placed
Footprints
- Pin 1 marked
- Polarity marked
- Matches datasheet
- Thermal pads OK
Placement
- Jumpers & debug accessible
- Filtering close to source
- Termination near targets
- SMPS loops minimized
- Caps & drivers close
- SMT top, THT bottom
Clearance
- Keep-outs respected
- Clearance by voltage
- No components at edge
Mechanical
- CAD file uploaded
- Clearance for connectors
- Harness radius OK
- Isolated mounting holes
- Board outline + enclosure defined
- Milled corners
Electrical
- All traces routed
- Analog/digital join once
- ERC passes
- Isolation barriers
Signal Integrity
- Ground gaps minimized
- No gaps under HS signals
- No stubs
- Differential pairs matched
- Terminated lines
- Short crystal lines
- Crystal guard ring
- No traces under sensitive or noisy parts
- RF via fencing OK
- Shielding can considered
Copper Pour
- Poured planes
- No high-Z paths
- No pour between IC pins
Traces
- Angled trace-pad
- Widths for current & heating
- No IC pin shorts
- Large vias for internal power
- Mitered bends or curves
Thermal
- Hot/cold components spaced
- Thermal vias in pads
Testing
- Test points added
- Analog test ground nearby
Silk screen
- Revision, date, serial space
- No silk over pads
- Text readable from 2 sides
- Font legibility
- Connector pinouts
- Fuse specs
- Group labels
- Functionality labels: test pts, LEDs, buttons, connectors

## Description V0.4 Fixes design errors from V0.3 --- ## Design Review Checklist <details> <summary>Process</summary> - [x] Commits in correct branch - [x] Schematic and PCB file names follow standard - [x] Export necessary review files (3D model, BOM, etc.) - [x] Update relevant system architecture documents - [x] Update project README page - [x] Simulations uploaded and outputs explained </details> <details> <summary>System</summary> - [x] Power - [x] Sufficient power supplied from upstream source - [x] Supply rated for necessary country specifications - [x] Estimated total worst-case power supply draw - [x] Connectors - [x] I/Os are specified - [x] Sufficient Current and Voltage rating - [x] Mating connectors have matching pinout - [x] Same contact material specified for mating connectors - [x] Testing - [x] Test procedure written - [x] Environmental - [x] Specified min/max operating temperature - [x] Specified min/max storage temperature - [x] Specified min/max humidity - [x] ROHS compliance requirement review </details> <details> <summary>Components</summary> - [x] Unpopulated components are denoted DNI - [x] Components meet environmental specifications - [x] All components have quantity, reference designator and description - [x] Suggested and alternate manufacturers listed - [x] Price and stock checked for each component - [x] Component derating - [x] Voltage - [x] Current - [x] Power at worst-case operating temperature - [x] Temperature at worst-case power </details> <details> <summary>Schematics</summary> - [x] Document - [x] Dot on each connection - [x] No four-point connections - [x] Title block completed for each sheet - [x] All components have reference designators and values - [x] Multi-part components don't have unplaced symbols - [x] Page title present and consistent on all pages if not in title block - [x] Symbols identify open collector/drain pins and internal pulled up/down pins - [x] Pin names and attributes match design usage - [x] Reference designators follow standard - [x] External I/O - [x] EMI filtered - [x] ESD protection - [x] Unused inputs terminated - [x] Microcontrollers / ICs - [x] Controlled power-up state - [x] Reset filtered - [x] Bypass caps - [x] Oscillator startup - [x] Pullups on OC pins - [x] Logic levels verified - [x] No-connect pins labeled - [x] Termination for clock lines - [x] Input voltage risks & latchup - [x] Datasheet errata reviewed - [ ] Busses - [ ] UART TX->RX and RX<-TX - [ ] I2C pullups [per capacitance](https://www.ti.com/lit/an/slva689/slva689.pdf) - [ ] Timing reviewed - [x] Analog - [x] Rail availability - [x] Amp stability - [x] Rise/fall timing - [ ] General - [ ] Bulk capacitance - [ ] Polarized components - [ ] Reverse voltage checked - [ ] Derating for MTBF - [x] LDOs have sufficient caps - [ ] Comparator timing - [ ] Opamp input range - [ ] Custom pin numbers verified - [ ] BJT reverse current - [ ] Net naming consistent - [ ] Debug resources added </details> <details> <summary>PCB</summary> - [x] Manufacturing - [x] `fab` layer info present - [x] Plating - [x] Stack-up - [x] Trace/space - [x] Hole size - [x] PCB/silkscreen color - [x] Impedance - [x] Blind/buried vias - [x] Panelization and routing - [x] Drill table - [x] Tolerance margins - [x] Power planes spaced - [x] Solder paste OK - [x] Fiducials placed - [x] Footprints - [x] Pin 1 marked - [x] Polarity marked - [x] Matches datasheet - [x] Thermal pads OK - [x] Placement - [x] Jumpers & debug accessible - [x] Filtering close to source - [x] Termination near targets - [x] SMPS loops minimized - [x] Caps & drivers close - [x] SMT top, THT bottom - [x] Clearance - [x] Keep-outs respected - [x] Clearance by voltage - [x] No components at edge - [x] Mechanical - [x] CAD file uploaded - [x] Clearance for connectors - [x] Harness radius OK - [x] Isolated mounting holes - [x] Board outline + enclosure defined - [x] Milled corners - [x] Electrical - [x] All traces routed - [x] Analog/digital join once - [x] ERC passes - [x] Isolation barriers - [x] Signal Integrity - [x] Ground gaps minimized - [x] No gaps under HS signals - [x] No stubs - [x] Differential pairs matched - [x] Terminated lines - [x] Short crystal lines - [x] Crystal guard ring - [x] No traces under sensitive or noisy parts - [x] RF via fencing OK - [x] Shielding can considered - [x] Copper Pour - [x] Poured planes - [x] No high-Z paths - [x] No pour between IC pins - [x] Traces - [x] Angled trace-pad - [x] Widths for current & heating - [x] No IC pin shorts - [x] Large vias for internal power - [x] Mitered bends or curves - [x] Thermal - [x] Hot/cold components spaced - [x] Thermal vias in pads - [x] Testing - [x] Test points added - [x] Analog test ground nearby - [ ] Silk screen - [x] Revision, date, serial space - [x] No silk over pads - [ ] Text readable from 2 sides - [ ] Font legibility - [ ] Connector pinouts - [ ] Fuse specs - [ ] Group labels - [ ] Functionality labels: test pts, LEDs, buttons, connectors </details>

allspice-carah added 2 commits 2026-03-17 17:06:47 +00:00

A few design changes b08f1b8753

introduces additional schematic changes

Run Connections Checker / connections-checker (pull_request) Successful in 33m0s

Details

b09435216b

allspice-carah requested review from DRCY 2026-03-17 17:06:51 +00:00

DRCYAI commented

2026-03-17 17:07:10 +00:00

DRCY has reviewed this Design Review, and there should be a review posted below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

DRCY has reviewed this Design Review, and there should be a review posted below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results.

DRCYAI reviewed 2026-03-17 19:59:49 +00:00

DRCYAI left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 169 component(s) to review, and found 8 potential issue(s) in 13 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Warning

At least one netlist for this review was generated from a PCB layout file. If
the PCB is out of sync with the schematic, the analysis may be inaccurate.
Please ensure your PCB is up to date before relying on these results.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

U1 - TPS54531 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
2	VIN	VPWR	❌	VIN pin connected to VPWR rail with inadequate input decoupling capacitance. Datasheet recommends 10µF ceramic capacitor close to VIN pin, but only 10nF (C71) is nearby with bulk capacitance far away. Pin 2 (VIN) is connected to net VPWR (from schematic) VPWR is the main input power rail derived from VPWR_IN through fuse F2 (from schematic) C71 (10nF 0402 50V X7R) is the closest capacitor to U1 on the VPWR net (from schematic) C199, C202, and C203 (each 100nF 0603) are connected to VPWR but located far from U1 (from schematic) Total ceramic capacitance on VPWR near U1 is approximately 10nF from C71 plus 300nF from distant capacitors, totaling ~310nF (reasoning) Datasheet specifies input voltage range of 3.5V to 28V (from datasheet TPS54531DDAR, page 4) Datasheet requires input decoupling capacitor with typical recommended value of 10µF high-quality ceramic type X5R or X7R (from datasheet TPS54531DDAR, page 14) Datasheet design example uses two 4.7-µF capacitors for input decoupling, totaling 9.4µF (from datasheet TPS54531DDAR, page 15) Datasheet layout guidelines state VIN pin must be bypassed to ground with low-ESR ceramic bypass capacitor with optimum placement closest to VIN pins (from datasheet TPS54531DDAR, page 23) Datasheet emphasizes minimizing loop area formed by bypass capacitor connections, VIN pin, and anode of catch diode (from datasheet TPS54531DDAR, page 14) The total input capacitance of approximately 310nF is significantly less than the recommended 10µF (approximately 32× smaller) (reasoning) Insufficient input decoupling capacitance can lead to increased input voltage ripple, potential instability, poor transient response, increased EMI, and potential damage to the IC (reasoning) Recommendation: Add 10µF or greater ceramic capacitor (X5R or X7R) directly at U1 VIN pin with minimal loop area to meet datasheet requirements (reasoning)
1	BOOT	NetC1_1	✅	BOOT pin correctly connected to PH pin through 100nF bootstrap capacitor C1.
3	EN	NetR2_2	✅	EN pin correctly connected to UVLO voltage divider (R11/R2) and comparator outputs for enable control and undervoltage lockout.
4	SS	NetC171_2	✅	SS pin correctly connected to 10nF soft-start capacitor C171 to ground, matching datasheet example for 4ms soft-start time.
5	VSNS	NetC3_1	✅	VSNS pin correctly connected to output voltage feedback divider (R1/R5) for 5V output regulation. Sensing point is before current sense resistor R148, which causes output voltage to be slightly lower under load but is intentional for current monitoring.
6	COMP	NetC150_2	✅	COMP pin correctly connected to compensation network with R10 (37.4kΩ), C150 (2.2nF), and C151 (22pF), matching datasheet example values exactly.
7	GND	GND	✅	GND pin correctly connected to ground plane.
8	PH	NetC1_2	✅	PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1.
9	PAD	GND	✅	PowerPAD correctly connected to ground for thermal and electrical performance.

L1 - 4.7uH 10A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC1_2	✅	Inductor input correctly connected to switching node (PH pin of U1) for buck converter operation.
2	2	NetC3_2	✅	Inductor output correctly connected to buck converter output node before current sense resistor R148.

D2 - SK54B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Catch diode correctly connected with anode to GND and cathode to switching node for freewheeling current path in buck converter.
K	CATHODE	NetC1_2	✅	Catch diode correctly connected with anode to GND and cathode to switching node for freewheeling current path in buck converter.

R148 - 0.01R 1% 0805 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetC3_2	✅	Current sense resistor correctly placed between buck converter output and +5VCC rail for current monitoring by U19. At 5A, voltage drop is 50mV and power dissipation is 0.25W, within the 0.5W rating.
2	2	+5VCC	✅	Current sense resistor correctly placed between buck converter output and +5VCC rail for current monitoring by U19. At 5A, voltage drop is 50mV and power dissipation is 0.25W, within the 0.5W rating.

U8 - MIC5353-3.3YMT-TR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	EN	+5VCC	✅	EN pin is connected to +5VCC, configuring the regulator for always-on operation when input power is present.
2	GND	GND	✅	GND pin is correctly connected to the ground net.
3	VIN	+5VCC	✅	VIN pin is connected to +5VCC supply with proper input capacitor C34 (1µF X5R ceramic), which is within the specified operating range of 2.6V to 6V.
4	VOUT	3.3VCC	✅	VOUT pin provides 3.3V output to the 3.3VCC net with proper output capacitor C24 (1µF X5R ceramic), matching the fixed 3.3V output version specified by the part number.
5	ADJ	unconnected-(NetU8_5)	✅	ADJ pin is correctly left unconnected, which is the proper configuration for the fixed voltage version of this regulator.
6	BYP	NetC26_1	✅	BYP pin is connected to a 100nF bypass capacitor (C26) to ground for reduced output noise and improved PSRR, matching the datasheet recommendation.
7	PAD	GND	✅	PAD (exposed heatsink pad) is correctly connected to ground for proper thermal dissipation and electrical grounding.

U20 - 78L05 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	OUT	5V0_AUX	✅	OUT pin correctly provides regulated 5V output to the 5V0_AUX auxiliary power rail. Output is properly decoupled with two 100nF capacitors (C200, C201) providing 200nF total capacitance, which exceeds the minimum 0.1µF requirement specified in the datasheet.
2	GND	GND	✅	GND pin is correctly connected to the circuit ground reference as required by the datasheet.
3	IN	VPWR	✅	IN pin is correctly connected to VPWR (12-24VDC input rail) which is within the 30V maximum input voltage specification. Input capacitance of approximately 0.3µF from three parallel 100nF capacitors (C199, C202, C203) is slightly below the recommended 0.33µF but within acceptable tolerance. These capacitors are shared with other circuits on VPWR rather than being dedicated to U20, though this should not significantly impact stability.

U19 - INA381_ALT ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
5	CMPREF	NetR115_1	❌	CMPREF pin connected to voltage divider formed by R115 (15kΩ) and R119 (4.7kΩ), but the resistor values are incorrect and set the current limit to approximately 2.4A instead of the intended ~4A per schematic text note. The voltage divider produces 1.193V instead of the required 2.0V for 4A threshold. Pin 5 (CMPREF) is connected to net NetR115_1 (from schematic) R115 (15kΩ) connects NetR115_1 to 5V0_AUX (from schematic) R119 (4.7kΩ) connects NetR115_1 to GND (from schematic) CMPREF is the input reference to the comparator per datasheet (from datasheet INA381A2IDSGR, page 3) Voltage divider produces VCMPREF = 5V × (4.7kΩ / 19.7kΩ) = 1.193V (reasoning) INA381A2 has a gain of 50 V/V per datasheet (from datasheet INA381A2IDSGR, page 5) Current sense resistor R148 is 0.01Ω (10mΩ) (from schematic) Current limit threshold = VCMPREF / (Gain × RSENSE) = 1.193V / (50 × 0.01Ω) = 2.386A (reasoning) Schematic text note states 'Current Limiting for 5V rail (~4A)' (from schematic) For 4A threshold: VCMPREF_needed = 4A × 0.01Ω × 50 = 2.0V (reasoning) To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (reasoning) Current resistor values result in approximately 60% of the intended current limit (2.4A vs 4A) (reasoning) The incorrect threshold voltage is caused by wrong resistor values in R115 and R119 (reasoning)
1	IN+	NetC3_2	✅	IN+ pin correctly connected to supply side of current sense resistor R148 on net NetC3_2 for high-side current sensing.
2	Vs	5V0_AUX	✅	Vs pin correctly powered from 5V0_AUX auxiliary supply with appropriate decoupling capacitor C201 (100nF).
3	nALERT	NetR2_2	✅	nALERT pin correctly configured as open-drain output with 10kΩ pull-up resistor R11 to VPWR, connected to buck converter enable pin for overcurrent shutdown.
4	RESET	NetR102_1	✅	RESET pin correctly pulled high through R102 (1kΩ) to 5V0_AUX to configure latching mode operation as intended.
6	CMPIN	NetU19_6	✅	CMPIN and VOUT pins correctly connected together on net NetU19_6, forming the standard configuration with default 50mV comparator hysteresis.
7	VOUT	NetU19_6	✅	CMPIN and VOUT pins correctly connected together on net NetU19_6, forming the standard configuration with default 50mV comparator hysteresis.
8	IN-	+5VCC	✅	IN- pin correctly connected to load side of current sense resistor R148 on net +5VCC, completing the high-side current sensing configuration.
9	GND	GND	✅	GND pin correctly connected to system ground net GND.

R102 - RK73H1ETTP1001F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR102_1	✅	1kΩ pull-up resistor correctly configured between RESET pin (NetR102_1) and 5V0_AUX supply to enable latching mode operation of U19.
2	2	5V0_AUX	✅	1kΩ pull-up resistor correctly configured between RESET pin (NetR102_1) and 5V0_AUX supply to enable latching mode operation of U19.

R115 - 15K 1% 0402 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR115_1	❌	15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A. R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic) R115 pin 2 is connected to net 5V0_AUX (from schematic) R115 value is 15kΩ per schematic (from schematic) R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning) Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning) Schematic text note indicates intended current limit is ~4A (from schematic) For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning) To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning) With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning) Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning) The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)
2	2	5V0_AUX	❌	15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A. R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic) R115 pin 2 is connected to net 5V0_AUX (from schematic) R115 value is 15kΩ per schematic (from schematic) R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning) Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning) Schematic text note indicates intended current limit is ~4A (from schematic) For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning) To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning) With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning) Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning) The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)

R119 - 4.7k 1% 0402 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	❌	4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A. R119 pin 1 is connected to net GND (from schematic) R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic) R119 value is 4.7kΩ per schematic (from schematic) R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold (reasoning) Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning) Schematic text note indicates intended current limit is ~4A (from schematic) For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning) To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning) With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning) Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning) The 4.7kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)
2	2	NetR115_1	❌	4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A. R119 pin 1 is connected to net GND (from schematic) R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic) R119 value is 4.7kΩ per schematic (from schematic) R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold (reasoning) Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning) Schematic text note indicates intended current limit is ~4A (from schematic) For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning) To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning) With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning) Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning) The 4.7kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)

D43 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to ground for uni-directional TVS protection of the VMOTA motor power rail.
K	K	VMOTA	✅	Cathode is correctly connected to VMOTA motor power rail for transient voltage protection.

D22 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to ground for uni-directional TVS protection of the VPWR main power rail.
K	K	VPWR	✅	Cathode is correctly connected to VPWR main power rail for transient voltage protection.

F1 - 3557-2 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBED_IN	✅	Input side of fuse holder, connected to VBED_IN from barrier connector J3 pin 7. This is the correct configuration for fuse input providing overcurrent protection for the heated bed power rail.
2	2	VBED	✅	Output side of fuse holder, connected to VBED rail which supplies power to heated bed loads and protection circuitry. This is the correct configuration for fuse output.

D78 - SMAJ24A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode pin correctly connected to GND for uni-directional TVS protection of the VBED positive rail. This is the proper configuration for transient voltage suppression.
K	K	VBED	✅	Cathode pin correctly connected to VBED rail for transient voltage protection of the heatbed power supply. The 24V TVS rating is appropriate for the 12-24VDC input range.

F2 - 3557-2 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR_IN	✅	Input side of fuse, connected to VPWR_IN from main power input connector J3 pin 5, providing overcurrent protection for the VPWR rail.
2	2	VPWR	✅	Output side of fuse, connected to VPWR rail which distributes power to the TPS54531 buck regulator, 78L05 LDO, comparators, and external loads through header P1. Protected by TVS diode D22 and filtered by multiple capacitors.

D21 - SMAJ24A ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	VMOTE	❌	The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic) SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet SMAJ24A, page 1) The cathode is marked with a color band in uni-directional configuration (from datasheet SMAJ24A, page 1) For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet SMAJ24A, page 3) During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning) With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning) All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic) D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic) D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic) D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic) The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning) The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)
K	K	GND	❌	The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation. Pin A (Anode) is connected to net VMOTE (from schematic) Pin K (Cathode) is connected to net GND (from schematic) VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic) SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet SMAJ24A, page 1) The cathode is marked with a color band in uni-directional configuration (from datasheet SMAJ24A, page 1) For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet SMAJ24A, page 3) During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning) With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning) All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic) D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic) D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic) D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic) The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning) The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)

U21 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR157_1	✅	IN- (inverting input) is correctly connected to a reference voltage divider formed by R157 (130k from 5V0_AUX) and R158 (100k to GND), providing approximately 2.17V reference voltage.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the ground reference for the comparator.
3	IN+	NetR154_2	✅	IN+ (non-inverting input) is correctly connected to a voltage divider (R154/R155) that senses VMOTA, with hysteresis feedback through R156.
4	OUT	NetR2_2	✅	Output pin is correctly connected to NetR2_2 as an open-collector output with external pull-up resistor R11 (10k to VPWR) and pull-down R2 (1.4k to GND), forming a wired-OR enable signal.
5	VCC	VPWR	✅	VCC pin is correctly connected to VPWR, providing power to the comparator within its specified operating range.

R154 - 24k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOTA	✅	Connected to VMOTA, forming the top of the voltage divider that senses the motor supply voltage.
2	2	NetR154_2	✅	Connected to NetR154_2, the junction of the voltage divider and the IN+ input of U21.

R155 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the bottom of the voltage divider.
2	2	NetR154_2	✅	Connected to NetR154_2, the junction of the voltage divider and the IN+ input of U21.

R156 - 1M 5% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis.
2	2	NetR154_2	✅	Connected to NetR154_2 (IN+ of comparator), completing the hysteresis feedback path.

R157 - 130k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR157_1	✅	Connected to NetR157_1, the junction of the reference voltage divider and the IN- input of U21.
2	2	5V0_AUX	✅	Connected to 5V0_AUX, forming the top of the reference voltage divider. Note: Part number RC0402JR-07130KL indicates 5% tolerance (J code), but component specifies 1% tolerance; correct part number should be RC0402FR-07130KL (F code).

R158 - 100k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the bottom of the reference voltage divider.
2	2	NetR157_1	✅	Connected to NetR157_1, the junction of the reference voltage divider and the IN- input of U21.

U6 - AP331A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN-	NetR57_1	✅	Inverting input (IN-) connected to a precision reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k), providing a stable threshold reference of approximately 2.175V.
2	GND	GND	✅	Ground reference pin correctly connected to GND net.
3	IN+	NetR26_2	✅	Non-inverting input (IN+) connected to a voltage divider monitoring VMOTE through R26 (24k) and R56 (10k), with positive feedback via R28 (1M) for hysteresis, creating an undervoltage detection circuit with threshold around 7.4V.
4	OUT	NetR2_2	✅	Open collector output correctly connected to NetR2_2 with external pull-up resistor R11 (10k to VPWR), wired-OR with U21 output to control enable signal for main power supply.
5	VCC	VPWR	✅	Power supply pin (Vcc) correctly connected to VPWR, which is within the comparator's operating voltage range of 2-36V.

R26 - 24k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOTE	✅	Connected to VMOTE, forming the upper leg of the voltage divider that monitors the motor supply voltage.
2	2	NetR26_2	✅	Connected to NetR26_2, the midpoint of the voltage divider that feeds the non-inverting input of U6.

R56 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the lower leg of the voltage divider that monitors VMOTE.
2	2	NetR26_2	✅	Connected to NetR26_2, the midpoint of the voltage divider that feeds the non-inverting input of U6.

R28 - 1M 5% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis.
2	2	NetR26_2	✅	Connected to NetR26_2, providing positive feedback to the non-inverting input of U6 for hysteresis.

R57 - 130k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR57_1	✅	Connected to NetR57_1, the midpoint of the reference voltage divider that feeds the inverting input of U6.
2	2	5V0_AUX	✅	Connected to 5V0_AUX, forming the upper leg of the reference voltage divider.

R58 - 100k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the lower leg of the reference voltage divider.
2	2	NetR57_1	✅	Connected to NetR57_1, the midpoint of the reference voltage divider that feeds the inverting input of U6.

J3 - 10 Pos barrier ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VMOTE	❌	Connected to VMOTE net, which powers motors 5-8. However, the TVS diode D21 protecting this rail is connected backwards (anode on VMOTE, cathode on GND), which will not provide proper overvoltage protection. Pin 1 is connected to the VMOTE net (from schematic) VMOTE powers motors 5-8 based on nearby text annotation (from schematic) VMOTE is protected by TVS diode D21 (SMAJ24A) (from schematic) D21 has its anode (A) connected to VMOTE and cathode (K) connected to GND (from schematic) For proper overvoltage protection, unidirectional TVS diodes should have cathode on the power rail and anode on ground to clamp positive voltage transients (reasoning) All other TVS diodes on the board (D43 on VMOTA, D22 on VPWR, D78 on VBED) are correctly oriented with cathode on power rail and anode on ground (from schematic) D21 is connected backwards compared to the other TVS diodes, which will prevent it from providing proper overvoltage protection and may conduct in normal operation (reasoning) D21 should be reversed to have cathode on VMOTE and anode on GND (reasoning) The barrier block is rated for 20A at 150V (UL Class C) and 10A at 300V (UL Class D), which is adequate for 12-24VDC motor power input (from datasheet 4DB-P108-10) Wire range is 12-22 AWG, suitable for high current motor power connections (from datasheet 4DB-P108-10)
2	2	GND	✅	Connected to GND. This provides a ground return path adjacent to the VMOTE power input on pin 1.
3	3	VMOTA	✅	Connected to VMOTA net, which powers motors 1-4. The connection is correct and properly protected.
4	4	GND	✅	Connected to GND. This provides a ground return path adjacent to the VMOTA power input on pin 3.
5	5	VPWR_IN	✅	Connected to VPWR_IN net, which is the input for fans, expansion, heaters, and logic power. The connection is correct.
6	6	GND	✅	Connected to GND. This provides a ground return path adjacent to the VPWR_IN power input on pin 5.
7	7	VBED_IN	✅	Connected to VBED_IN net, which is the input for heated bed power. The connection is correct.
8	8	GND	✅	Connected to GND. This provides a ground return path adjacent to the VBED_IN power input on pin 7.
9	9	VBED	✅	Connected to VBED net, which is the fused heated bed power output. The connection is correct, though having both VBED_IN (pin 7) and VBED (pin 9) on the same connector is an unusual design choice.
10	10	HTBD-OUT	✅	Connected to HTBD-OUT net, which appears to be a heated bed control output signal. The net only connects to this pin on the visible schematic page, suggesting it may connect to circuitry on another page or be an external output.

P1 - Header 4X2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	Both pins connected to VFAN net, which provides fan power. VFAN is derived from VPWR through 0R jumper R103.
3	3	VFAN	✅	Both pins connected to VFAN net, which provides fan power. VFAN is derived from VPWR through 0R jumper R103.
2	2	GND	✅	Both pins connected to GND, providing ground return paths for the VFAN outputs on pins 1 and 3.
4	4	GND	✅	Both pins connected to GND, providing ground return paths for the VFAN outputs on pins 1 and 3.
5	5	VPWR	✅	Both pins connected to VPWR net, which provides main power for fans, expansion, heaters, and logic circuits.
7	7	VPWR	✅	Both pins connected to VPWR net, which provides main power for fans, expansion, heaters, and logic circuits.
6	6	GND	✅	Both pins connected to GND, providing ground return paths for the VPWR outputs on pins 5 and 7.
8	8	GND	✅	Both pins connected to GND, providing ground return paths for the VPWR outputs on pins 5 and 7.

D23 - 5988170107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD23_A	✅	LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ), forming a power indicator circuit for the 3.3V rail.
C	C	GND	✅	LED cathode is correctly connected to GND, providing the return path for the indicator LED circuit.

R33 - RK73H1ETTP1001F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD23_A	✅	Resistor terminal connects to LED D23 anode, providing current limiting for the power indicator LED.
2	2	3.3VCC	✅	Resistor terminal connects to 3.3VCC power rail, sourcing current for the LED indicator circuit.

R11 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR2_2	✅	Connected to NetR2_2, forming the middle node of a voltage divider that provides enable voltage to U1 and allows comparator-based UVLO protection.
2	2	VPWR	✅	Connected to VPWR, the main input power rail, forming the top of the enable voltage divider.

R2 - 1.4k 1% 0402 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, forming the bottom of the enable voltage divider.
2	2	NetR2_2	✅	Connected to NetR2_2, forming the middle node of the voltage divider that sets the enable voltage for U1.

R103 - 0R 0603 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VPWR	✅	Pin 1 connects to VPWR, the main power rail that supplies the buck regulator, comparators, and LDO. This is one terminal of the 0-ohm jumper.
2	2	VFAN	✅	Pin 2 connects to VFAN, which supplies power to fan connectors on header P1. This is the other terminal of the 0-ohm jumper.

J8 - USB-B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS	NetC43_2	✅	VBUS pin correctly connected to USB power input with ESD protection, filtering capacitor, and ferrite bead to VUSB supply.
2	DM	DM	✅	D- data line correctly connected to ESD protection device for USB differential signaling.
3	DP	DP	✅	D+ data line correctly connected to ESD protection device for USB differential signaling.
4	GND	USB_GND	✅	Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology.
5	SHLD	USB_GND	✅	Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology.
6	SHLD	USB_GND	✅	Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology.

D27 - PRTR5V0U2F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Net	Correct?	Analysis
1	DM	✅	I/O1 pin correctly connected to USB D- data line from connector for ESD protection.
2	USB_GND	✅	Ground pin correctly connected to isolated USB ground domain.
3	DP	✅	I/O2 pin correctly connected to USB D+ data line from connector for ESD protection.
4	NetD27_4	✅	I/O2 pin correctly connected through common mode choke to isolated USB interface.
5	NetC43_2	✅	VCC pin correctly connected to USB VBUS for supply-referenced ESD protection.
6	NetD27_6	✅	I/O1 pin correctly connected through common mode choke to isolated USB interface.

D26 - RSB39VTE-17 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Bidirectional TVS diode correctly placed between USB_GND and GND for isolation barrier overvoltage protection.
C	C	USB_GND	✅	Bidirectional TVS diode correctly placed between USB_GND and GND for isolation barrier overvoltage protection.

L5 - DLW21HN900SQ2L ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Net	Correct?	Analysis
1	NetL5_1	✅	Common mode choke output for D+ line, correctly connected through series resistor to USB isolator positive data input.
2	NetD27_4	✅	Common mode choke input for D+ line, correctly connected to ESD protection device output.
3	NetD27_6	✅	Common mode choke input for D- line, correctly connected to ESD protection device output.
4	NetL5_4	✅	Common mode choke output for D- line, correctly connected through series resistor to USB isolator negative data input.

U9 - ADuM4160 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUS1	VUSB	✅	VBUS1 is correctly connected to VUSB, which provides 5V power from the USB bus through protection circuitry including ferrite bead FB29 and TVS diode D27.
2	GND1	USB_GND	✅	GND1 pins are correctly connected to USB_GND, providing isolated ground reference for the upstream side of the isolator.
8	GND1	USB_GND	✅	GND1 pins are correctly connected to USB_GND, providing isolated ground reference for the upstream side of the isolator.
3	VDD1	VDD1	✅	VDD1 is correctly connected to the VDD1 net, which is the regulated 3.3V output from the internal LDO regulator with proper bypass capacitor.
4	PDEN	VDD1	✅	PDEN is correctly tied to VDD1 for standard operation, enabling normal downstream pull-down resistor operation.
5	SPU	VDD1	✅	SPU is correctly tied high to VDD1, selecting full speed operation for the upstream buffer and matching the SPD pin configuration.
6	UD- 1	UD_N	✅	UD- is correctly connected to the upstream USB D- line through series termination resistor R43 (24Ω) as required for full speed operation.
7	UD+ 1	UD_P	✅	UD+ is correctly connected to the upstream USB D+ line through series termination resistor R46 (24Ω) as required for full speed operation.
9	GND2	GND	✅	GND2 pins are correctly connected to system GND, providing isolated ground reference for the downstream side of the isolator.
15	GND2	GND	✅	GND2 pins are correctly connected to system GND, providing isolated ground reference for the downstream side of the isolator.
10	UD+ 2	UI_P	✅	DD+ (labeled UD+ 2 in schematic) is correctly connected to the downstream USB D+ line through series termination resistor R47 (24Ω) to the microcontroller.
11	UD- 2	UI_N	✅	DD- (labeled UD- 2 in schematic) is correctly connected to the downstream USB D- line through series termination resistor R45 (24Ω) to the microcontroller.
12	PIN	3.3VCC	✅	PIN is correctly connected to 3.3VCC, which enables the upstream pull-up resistor for USB enumeration. The net naming (3.3VCC vs +3.3VCC) suggests this may be intentional for delayed enumeration control, though both configurations are functionally acceptable.
13	SPD	3.3VCC	✅	SPD is correctly connected to 3.3VCC to select full speed operation for the downstream buffer, matching the SPU pin configuration.
14	VDD2	+3.3VCC	✅	VDD2 is correctly connected to +3.3VCC with proper bypass capacitors, providing 3.3V power supply for the downstream side of the isolator.
16	VBUS2	+3.3VCC	✅	VBUS2 is correctly connected to +3.3VCC along with VDD2, configuring the downstream side for 3.3V operation and bypassing the internal regulator.

R43 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_N	✅	Resistor terminal 1 is correctly connected to UD_N from the USB isolator upstream D- pin (U9 pin 6).
2	2	NetL5_4	✅	Resistor terminal 2 is correctly connected to NetL5_4, which goes to the common mode choke L5 and then to the USB connector D- line.

R46 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UD_P	✅	Resistor terminal 1 is correctly connected to UD_P from the USB isolator upstream D+ pin (U9 pin 7).
2	2	NetL5_1	✅	Resistor terminal 2 is correctly connected to NetL5_1, which goes to the common mode choke L5 and then to the USB connector D+ line.

R47 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_P	✅	Resistor terminal 1 is correctly connected to UMCU_P, which goes to the microcontroller USB D+ pin (U11B pin 37, DHSDP).
2	2	UI_P	✅	Resistor terminal 2 is correctly connected to UI_P from the USB isolator downstream D+ pin (U9 pin 10).

R45 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	UMCU_N	✅	Resistor terminal 1 is correctly connected to UMCU_N, which goes to the microcontroller USB D- pin (U11B pin 38, DHSDM).
2	2	UI_N	✅	Resistor terminal 2 is correctly connected to UI_N from the USB isolator downstream D- pin (U9 pin 11).

U11B - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
37	DHSDP	UMCU_P	❌	The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance. Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic) Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic) Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic) Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic) UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic) DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic) The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet ATSAM3X8EA-AU, page 1401-1402) Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning) The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning) Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning) Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning) Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning) Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)
38	DHSDM	UMCU_N	❌	The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance. Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic) Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic) Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic) Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic) UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic) DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic) The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet ATSAM3X8EA-AU, page 1401-1402) Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning) The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning) Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning) Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning) Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning) Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)
42	DFSDP	NetR48_1	❌	The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance. Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic) Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic) Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic) Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic) UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic) DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic) The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet ATSAM3X8EA-AU, page 1401-1402) Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning) The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning) Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning) Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning) Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning) Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)
43	DFSDM	NetR42_1	❌	The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance. Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic) Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic) Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic) Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic) UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic) DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8) The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic) The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet ATSAM3X8EA-AU, page 1401-1402) Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning) The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning) Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning) Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning) Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning) Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)
35	XOUT	NetC41_2	✅	XOUT is correctly connected to the 12MHz crystal oscillator output through a 3pF load capacitor.
36	XIN	NetC42_2	✅	XIN is correctly connected to the 12MHz crystal oscillator input through a 3pF load capacitor.
39	VBUS	VBUS_UC	✅	VBUS is correctly connected to a USB bus power detection circuit that provides isolated sensing of USB power presence.
40	VBG	NetC49_1	✅	VBG is correctly connected with a 6.8kΩ ±1% resistor and 10pF capacitor to ground, exactly matching the datasheet specification.
46	JTAGSEL	GND	✅	JTAGSEL is correctly connected to GND for normal JTAG operation mode.
47	NRSTB	RESET	✅	NRSTB is correctly connected to the RESET net for asynchronous microcontroller reset.
48	XIN32	XIN32	✅	XIN32 is correctly connected to the 32.768 kHz slow clock oscillator input.
49	XOUT32	XOUT32	✅	XOUT32 is correctly connected to the 32.768 kHz slow clock oscillator output.
50	SHDN	SHDN	✅	SHDN is correctly connected as an output pin indicating device shutdown state.
51	TST	GND	✅	TST is correctly connected to GND for normal operation (not test mode).
53	FWUP	NetR51_1	✅	FWUP is correctly connected with a 100kΩ pull-up resistor to +3.3VCC as required by the datasheet.
69	NRST	NetC169_1	✅	NRST is correctly connected with a 100nF filter capacitor and 100Ω series resistor for reset signal conditioning.
75	ADVREF	VDDANA	✅	ADVREF is correctly connected to VDDANA for ADC and DAC voltage reference.

R48 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR48_1	✅	R48 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R48 should be removed or marked as DNI.
2	2	UMCU_P	✅	R48 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R48 should be removed or marked as DNI.

R42 - CRCW040224R0FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR42_1	✅	R42 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R42 should be removed or marked as DNI.
2	2	UMCU_N	✅	R42 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R42 should be removed or marked as DNI.

U18 - OPTO SO-4 OPNDRN OUT ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	A	NetR152_2	✅	Anode of optocoupler LED correctly connected to VUSB through 1kΩ current limiting resistor R152, providing approximately 3.75mA LED current for USB power detection.
2	K	USB_GND	✅	Cathode of optocoupler LED correctly connected to USB_GND to complete the LED circuit on the isolated USB side.
3	E	GND	✅	Emitter of phototransistor correctly connected to GND (system ground) to provide reference for the output side of the optocoupler.
4	C	NetQ8_1	✅	Collector of phototransistor correctly connected to Q8 base through net NetQ8_1 with 6.8kΩ pull-up resistor R151. When LED is on, phototransistor pulls base low to turn off Q8.

Q8 - MMBT3904_SOT523 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B	NetQ8_1	✅	Base correctly connected to optocoupler collector output through net NetQ8_1 with 6.8kΩ pull-up resistor R151. Receives control signal from optocoupler to switch VBUS_UC.
2	E	GND	✅	Emitter correctly connected to GND for standard common-emitter switch configuration.
3	C	VBUS_UC	✅	Collector correctly connected to VBUS_UC with 6.8kΩ pull-up resistor R150. Pulls VBUS_UC low when transistor is on (no USB power), allows pull-up when off (USB power present).

R152 - RK73H1ETTP1001F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	1kΩ current limiting resistor for optocoupler LED, correctly connected between VUSB and LED anode with appropriate value for approximately 3.75mA LED current.
2	2	NetR152_2	✅	1kΩ current limiting resistor for optocoupler LED, correctly connected between VUSB and LED anode with appropriate value for approximately 3.75mA LED current.

R150 - CRCW04026K80FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VBUS_UC	✅	6.8kΩ pull-up resistor for VBUS_UC signal, correctly connected between VBUS_UC and +5VCC with appropriate value.
2	2	+5VCC	✅	6.8kΩ pull-up resistor for VBUS_UC signal, correctly connected between VBUS_UC and +5VCC with appropriate value.

R151 - CRCW04026K80FKED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetQ8_1	✅	6.8kΩ pull-up resistor for Q8 base, correctly connected between Q8 base and +5VCC with appropriate value.
2	2	+5VCC	✅	6.8kΩ pull-up resistor for Q8 base, correctly connected between Q8 base and +5VCC with appropriate value.

X1 - 405C35B12M00000 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	C1	NetC42_2	✅	Crystal pin C1 correctly connects to microcontroller XIN pin through load capacitor C42.
2	GND	GND	✅	Ground pins correctly connected to circuit ground for EMI suppression.
4	GND	GND	✅	Ground pins correctly connected to circuit ground for EMI suppression.
3	C2	NetC41_2	✅	Crystal pin C2 correctly connects to microcontroller XOUT pin through load capacitor C41.

C41 - 3pF 0603 50V NP0 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	❌	Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF. Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic) Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic) This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1) The connection topology is correct for a crystal oscillator load capacitor (reasoning) The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1) The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet 405C35B12M00000, page 1) For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning) With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning) This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning) To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning) The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning) Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)
2	2	NetC41_2	❌	Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF. Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic) Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic) This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1) The connection topology is correct for a crystal oscillator load capacitor (reasoning) The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1) The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet 405C35B12M00000, page 1) For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning) With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning) This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning) To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning) The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning) Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)

C42 - 3pF 0603 50V NP0 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	❌	Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF. Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 (from schematic) Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) (from schematic) This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1) The connection topology is correct for a crystal oscillator load capacitor (reasoning) The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1) C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required (reasoning) The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side (from datasheet 405C35B12M00000, page 1) The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning) Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)
2	2	NetC42_2	❌	Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF. Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 (from schematic) Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) (from schematic) This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1) The connection topology is correct for a crystal oscillator load capacitor (reasoning) The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1) C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required (reasoning) The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side (from datasheet 405C35B12M00000, page 1) The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning) Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)

FB29 - FERRITE 120R 3A 0603 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VUSB	✅	Connected to VUSB, the filtered USB power rail on the isolated side of the USB interface. This is the output side of the ferrite bead providing filtered power to the USB isolator and related circuitry.
2	2	NetC43_2	✅	Connected to NetC43_2, which includes the raw VBUS from USB connector J8 pin 1. This is the input side of the ferrite bead receiving unfiltered USB power from the connector.

JP1 - SJ ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Solder jumper between +5VCC (pin 1) and VUSB (pin 2) allowing optional powering of the system from USB. Pin 1 connects to the main system 5V rail, while pin 2 connects to the filtered USB power after ferrite bead FB29.
2	2	VUSB	✅	Solder jumper between +5VCC (pin 1) and VUSB (pin 2) allowing optional powering of the system from USB. Pin 1 connects to the main system 5V rail, while pin 2 connects to the filtered USB power after ferrite bead FB29.

JP2 - SJ ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Solder jumper between GND (pin 1) and USB_GND (pin 2) as part of a configurable USB isolation scheme. Pin 1 connects to the main system ground, while pin 2 connects to the isolated ground domain on the USB connector side.
2	2	USB_GND	✅	Solder jumper between GND (pin 1) and USB_GND (pin 2) as part of a configurable USB isolation scheme. Pin 1 connects to the main system ground, while pin 2 connects to the isolated ground domain on the USB connector side.

U11A - ATML-ATSAM3X-LQFP-144 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
29	PB29/TDI	TDO/SWO	❌	JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net. Pin 29 is PB29/TDI (Test Data In) (from schematic) Pin 29 is connected to net TDO/SWO (from schematic) Pin 30 is PB30/TDO/TRACESWO (Test Data Out) (from schematic) Pin 30 is connected to net TDI (from schematic) PB29 should function as TDI (Test Data In) per datasheet (from datasheet ATSAM3X8EA-AU, page 8) PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet (from datasheet ATSAM3X8EA-AU, page 8) JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) (from schematic) JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) (from schematic) The TDI and TDO pins are swapped, preventing proper JTAG debugging (reasoning) Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO (reasoning)
30	PB30/TDO/TRACESWO	TDI	❌	JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net. Pin 29 is PB29/TDI (Test Data In) (from schematic) Pin 29 is connected to net TDO/SWO (from schematic) Pin 30 is PB30/TDO/TRACESWO (Test Data Out) (from schematic) Pin 30 is connected to net TDI (from schematic) PB29 should function as TDI (Test Data In) per datasheet (from datasheet ATSAM3X8EA-AU, page 8) PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet (from datasheet ATSAM3X8EA-AU, page 8) JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) (from schematic) JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) (from schematic) The TDI and TDO pins are swapped, preventing proper JTAG debugging (reasoning) Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO (reasoning)
1	PB26/CTS0/TCLK0/WKUP15	STEP6	✅	PB26 configured as GPIO output for stepper motor step control (STEP6).
2	PA9/UTXD/PWMH3	PA9_UTXD	✅	PA9 configured as UTXD for UART transmit.
3	PA10/RXD0/DATRG/WKUP5	DIAG7	✅	PA10 configured as GPIO input for diagnostic signal (DIAG7).
4	PA11/TXD0/ADTRG/WKUP6	DIAG8	✅	PA11 configured as GPIO input for diagnostic signal (DIAG8).
5	PA12/RXD1/PWML1/WKUP7	PA12_RXD1	✅	PA12 configured as RXD1 for USART1 receive.
6	PA13/TXD1/PWMH2	PA13_TXD1	✅	PA13 configured as TXD1 for USART1 transmit.
7	PA14/RTS1/TK	PA14_RTS1	✅	PA14 configured as RTS1 for USART1 flow control.
8	PA15/CTS1/TF/WKUP8	PA15_CTS1	✅	PA15 configured as CTS1 for USART1 flow control.
9	PA17/TWD0/SPCK0	PA17_SDA	✅	PA17 configured as TWD0 (I2C SDA) with proper pull-up resistor.
13	PD0/A10/MCDA4	M_nCS7	✅	PD0 configured as GPIO output for chip select (M_nCS7).
14	PD1/A11/MCDA5	DIR8	✅	PD1 configured as GPIO output for stepper motor direction control (DIR8).
15	PD2/A12/MCDA6	M_nCS8	✅	PD2 configured as GPIO output for chip select (M_nCS8).
16	PD3/A13/MCDA7	STEP8	✅	PD3 configured as GPIO output for stepper motor step control (STEP8).
17	PD4/A14/TXD3	MIN_ES1	✅	PD4 configured as GPIO input for minimum endstop (MIN_ES1).
18	PD5/A15/RXD3	MAX_ES2	✅	PD5 configured as GPIO input for maximum endstop (MAX_ES2).
19	PD6/A16/BA0/PWMFI2	MIN_ES2	✅	PD6 configured as GPIO input for minimum endstop (MIN_ES2).
20	PD7/A17/BA1/TIOA8	TACH_3	✅	PD7 configured as GPIO input for tachometer (TACH_3).
21	PD8/A21/NANDALE/TIOB8	TACH_2	✅	PD8 configured as GPIO input for tachometer (TACH_2).
22	PD9/A22/NANDCLE/TCLK8	MAX_ES3	✅	PD9 configured as GPIO input for maximum endstop (MAX_ES3).
23	PA0/CANTX0/PWML3	PA0_CANTX0	✅	PA0 configured as CANTX0 for CAN bus transmit.
24	PA1/CANRX0/PCK0/WKUP0	PA1_CANRX0	✅	PA1 configured as CANRX0 for CAN bus receive.
25	PA5/TIOA2/PWMFI0/WKUP2	PA5_PWM	✅	PA5 configured as GPIO output for PWM control.
26	PA7/TCLK2/NCS1/WKUP3	MIN_ES3	✅	PA7 configured as GPIO input for minimum endstop (MIN_ES3).
27	PA8/URXD/PWMH0/WKUP4	PA8_URXD	✅	PA8 configured as URXD for UART receive.
28	PB28/TCK/SWCLK	TCK/SWDCLK	✅	PB28 configured as TCK/SWCLK for JTAG/SWD debugging.
31	PB31/TMS/SWDIO	TMS/SWDIO	✅	PB31 configured as TMS/SWDIO for JTAG/SWD debugging.
32	PD10/NWR1/NBS1	MAX_ES1	✅	PD10 configured as GPIO input for maximum endstop (MAX_ES1).
55	PC1	LED_Y	✅	PC1 configured as GPIO output for yellow LED control.
59	PC2/D0/PWML0	PC2_PWML0	✅	PC2 configured as PWML0 for PWM output.
60	PC3/D1/PWMH0	LED_R	✅	PC3 configured as GPIO output for red LED control.
63	PC5/D3/PWMH1	DIAG1	✅	PC5 configured as GPIO input for diagnostic signal (DIAG1).
64	PC6/D4/PWML2	DIR1	✅	PC6 configured as GPIO output for stepper motor direction control (DIR1).
65	PC7/D5/PWMH2	STEP1	✅	PC7 configured as GPIO output for stepper motor step control (STEP1).
66	PC8/D6/PWML3	PC8_PWML3	✅	PC8 configured as PWML3 for PWM output.
67	PC9/D7/PWMH3	DRV_EN	✅	PC9 configured as GPIO output for driver enable signal (DRV_EN).
68	PB27/NCS3/TIOB0	PB27_TIOB0	✅	PB27 configured as TIOB0 for timer I/O.
70	PA18/TWCK0/A20/WKUP9	PA18_SCL	✅	PA18 configured as TWCK0 (I2C SCL) with proper pull-up resistor.
71	PA19/MCCK/PWMH1	MCCK	✅	PA19 configured as MCCK for SD card clock.
72	PA20/MCCDA/PWML2	MCCDA	✅	PA20 configured as MCCDA for SD card command/data.
76	PB15/CANRX1/PWMH3/DAC0/WKUP12	Fan3	✅	PB15 configured as DAC0 or PWM for fan control (Fan3).
77	PB16/TCLK5/PWML0/DAC1	Fan4	✅	PB16 configured as DAC1 or PWM for fan control (Fan4).
78	PA16/SPCK1/TD/AD7	PA16	✅	PA16 configured as general purpose I/O.
79	PA24/MCDA3/PCK1/AD6	MCDA3	✅	PA24 configured as MCDA3 for SD card data line 3.
80	PA23/MCDA2/TCLK4/AD5	MCDA2	✅	PA23 configured as MCDA2 for SD card data line 2.
81	PA22/MCDA1/TCLK3/AD4	MCDA1	✅	PA22 configured as MCDA1 for SD card data line 1.
82	PA6/TIOB2/NCS0/AD3	TC_nCS3	✅	PA6 configured as GPIO output for thermocouple chip select (TC_nCS3).
83	PA4/TCLK1/NWAIT/AD2	M_nCS1	✅	PA4 configured as GPIO output for motor driver chip select (M_nCS1).
84	PA3/TIOB1/PWMFI1/AD1/WKUP1	PA3_AD2	✅	PA3 configured as analog input AD1, but net is named PA3_AD2 which may be a naming inconsistency.
85	PA2/TIOA1/NANDRDY/AD0	TC_nCS4	✅	PA2 configured as GPIO output for thermocouple chip select (TC_nCS4).
86	PB12/TWD1/PWMH0/AD8	PB12_AD8	✅	PB12 configured as analog input AD8.
87	PB13/TWCK1/PWMH1/AD9	PB13_AD9	✅	PB13 configured as analog input AD9.
88	PB17/RF/PWML1/AD10	TC_nCS5	✅	PB17 configured as GPIO output for thermocouple chip select (TC_nCS5).
89	PB18/RD/PWML2/AD11	THERM_AN2	✅	PB18 configured as analog input AD11 for thermocouple (THERM_AN2).
90	PB19/RK/PWML3/AD12	THERM_AN1	✅	PB19 configured as analog input AD12 for thermocouple (THERM_AN1).
91	PB20/TXD2/SPI0_NPCS1/AD13	THERM_AN3	✅	PB20 configured as analog input AD13 for thermocouple (THERM_AN3).
92	PB21/RXD2/SPI0_NPCS2/AD14/WKUP13	SPIFLASH_CS	✅	PB21 configured as GPIO output for SPI flash chip select (SPIFLASH_CS).
93	PC11/D9/ERX2	DIAG2	✅	PC11 configured as GPIO input for diagnostic signal (DIAG2).
94	PC12/D10/ERX3	DIR2	✅	PC12 configured as GPIO output for stepper motor direction control (DIR2).
95	PC13/D11/ECOL	STEP2	✅	PC13 configured as GPIO output for stepper motor step control (STEP2).
96	PC14/D12/ERXCK	M_nCS2	✅	PC14 configured as GPIO output for motor driver chip select (M_nCS2).
97	PC15/D13/ETX2	DIAG3	✅	PC15 configured as GPIO input for diagnostic signal (DIAG3).
98	PC16/D14/ETX3	DIR3	✅	PC16 configured as GPIO output for stepper motor direction control (DIR3).
99	PC17/D15/ETXER	STEP3	✅	PC17 configured as GPIO output for stepper motor step control (STEP3).
100	PC18/NWR0/NWE/PWMH6	M_nCS3	✅	PC18 configured as GPIO output for motor driver chip select (M_nCS3).
101	PC19/NANDOE/PWMH5	DIAG4	✅	PC19 configured as GPIO input for diagnostic signal (DIAG4).
102	PC29/A8/TIOB7	TACH_4	✅	PC29 configured as GPIO input for tachometer (TACH_4).
103	PC30/A9/TCLK7	HOLD#	✅	PC30 configured as GPIO output for SPI flash hold signal (HOLD#).
107	PA21/MCDA0/PWML0	MCDA0	✅	PA21 configured as MCDA0 for SD card data line 0.
108	PA25/SPI0_MISO/A18	NetR83_2	✅	PA25 configured as SPI0_MISO with series termination resistor.
109	PA26/SPI0_MOSI/A19	NetR77_2	✅	PA26 configured as SPI0_MOSI with series termination resistor.
110	PA27/SPI0_SPCK/A20/WKUP10	NetR82_2	✅	PA27 configured as SPI0_SPCK with series termination resistor.
111	PA28/SPI0_NPCS0/PCK2/WKUP11	PA28_CS0	✅	PA28 configured as SPI0_NPCS0 for SPI chip select 0.
112	PA29/SPI0_NPCS1/NRD	PA29_CS	✅	PA29 configured as SPI0_NPCS1 for SPI chip select 1.
113	PB0/ETXCK/EREFCK	PB0_ETXCK	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
114	PB1/ETXEN	PB1_ETXEN	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
115	PB2/ETX0	PB2_ETX0	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
118	PB3/ETX1	STEP5	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
119	PB4/ECRSDV/ERXDV	M_nCS6	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
120	PB5/ERX0	M_nCS5	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
121	PB6/ERX1	DIR7	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
122	PB7/ERXER	MAX_ES4	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
123	PB8/EMDC	STEP7	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
127	PB9/EMDIO	TC_nCS2	✅	Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design.
116	PC4/D2/PWML1	DIR4	✅	PC4 configured as GPIO output for stepper motor direction control (DIR4).
117	PC10/D8/ECRS	STEP4	✅	PC10 configured as GPIO output for stepper motor step control (STEP4).
128	PB10/UOTGVBOF/A18	M_nCS4	✅	PB10 configured as GPIO output for motor driver chip select (M_nCS4).
129	PB11/UOTGID/A19	SDCD	✅	PB11 configured as GPIO input for SD card detect (SDCD).
130	PC0/ERASE	ERASE	✅	PC0 configured as ERASE pin for flash programming.
131	PC20/NANDWE/PWMH4	DIAG5	✅	PC20 configured as GPIO input for diagnostic signal (DIAG5).
132	PC21/A0/NBS0/PWML4	HEAT1	✅	PC21 configured as PWM output for heater control (HEAT1).
133	PC22/A1/PWML5	HEAT2	✅	PC22 configured as PWM output for heater control (HEAT2).
134	PC23/A2/PWML6	HEATBED	✅	PC23 configured as PWM output for heated bed control (HEATBED).
135	PC24/A3/PWML7	HEAT3	✅	PC24 configured as PWM output for heater control (HEAT3).
136	PC25/A4/TIOA6	FAN2	✅	PC25 configured as timer output for fan control (FAN2).
137	PC26/A5/TIOB6	FAN1	✅	PC26 configured as timer output for fan control (FAN1).
138	PC27/A6/TCLK6	TC_nCS1	✅	PC27 configured as GPIO output for thermocouple chip select (TC_nCS1).
139	PC28/A7/TIOA7	TACH_1	✅	PC28 configured as GPIO input for tachometer (TACH_1).
140	PB14/CANTX1/PWMH2	MIN_ES4	✅	PB14 configured as GPIO input for minimum endstop (MIN_ES4).
141	PB22/RTS2/PCK0	DIR5	✅	PB22 configured as GPIO output for stepper motor direction control (DIR5).
142	PB23/CTS2/SPI0_NPCS3/WKUP14	DIAG6	✅	PB23 configured as GPIO input for diagnostic signal (DIAG6).
143	PB24/SCK2/NCS2	DIR6	✅	PB24 configured as GPIO output for stepper motor direction control (DIR6).
144	PB25/RTS0/TIOA0	PB25_TIOA0	✅	PB25 configured as TIOA0 for timer I/O.

U11C - ATML-ATSAM3X-LQFP-144 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
10	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT (voltage regulator output).
45	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT (voltage regulator output).
61	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT (voltage regulator output).
104	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT (voltage regulator output).
124	VDDCORE	VDDOUT	✅	VDDCORE pins correctly connected to VDDOUT (voltage regulator output).
11	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO (I/O power supply).
62	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO (I/O power supply).
105	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO (I/O power supply).
125	VDDIO	3.3VIO	✅	VDDIO pins correctly connected to 3.3VIO (I/O power supply).
12	GND	GND	✅	GND pins correctly connected to ground.
58	GND	GND	✅	GND pins correctly connected to ground.
106	GND	GND	✅	GND pins correctly connected to ground.
126	GND	GND	✅	GND pins correctly connected to ground.
33	GNDPLL	GND	✅	GNDPLL pin correctly connected to ground.
34	VDDPLL	VDDPLL	✅	VDDPLL pin correctly connected with filtering through ferrite bead from VDDOUT.
41	VDDUTMI	VDDUTMI	✅	VDDUTMI pin correctly connected with filtering through ferrite bead from 3.3VCC.
44	GNDUTMI	GND	✅	GNDUTMI pin correctly connected to ground.
52	VDDBU	3.3VCC	✅	VDDBU pin correctly connected to 3.3VCC for backup power.
54	GNDBU	GND	✅	GNDBU pin correctly connected to ground.
56	VDDOUT	VDDOUT	✅	VDDOUT pin correctly connected with required decoupling capacitors.
57	VDDIN	3.3VCC	✅	VDDIN pin correctly connected to 3.3VCC with required decoupling capacitor.
73	VDDANA	VDDANA	✅	VDDANA pin correctly connected with filtering through ferrite bead from 3.3VCC.
74	GNDANA	GND	✅	GNDANA pin correctly connected to ground.

J4 - ARM Cortex JTAG-DEBUG Header ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
6	6	TDO/SWO	❌	TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning. Pin 6 is connected to the TDO/SWO net (from schematic) Pin 8 is connected to the TDI net (from schematic) The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic) The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic) ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning) In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning) The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning) The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning) The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning) To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)
8	8	TDI	❌	TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning. Pin 6 is connected to the TDO/SWO net (from schematic) Pin 8 is connected to the TDI net (from schematic) The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic) The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic) ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning) In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning) The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning) The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning) The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning) To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)
1	1	3.3VCC	✅	VTref (target reference voltage) pin correctly connected to 3.3VCC power rail to provide voltage reference to the debugger.
2	2	TMS/SWDIO	✅	TMS/SWDIO pin correctly connected to microcontroller PB31 with appropriate 100K pull-up resistor.
3	3	GND	✅	Ground pin correctly connected to GND net.
4	4	TCK/SWDCLK	✅	TCK/SWDCLK pin correctly connected to microcontroller PB28 with appropriate 100K pull-up resistor.
5	5	GND	✅	Ground pin correctly connected to GND net.
7	7	unconnected-(NetJ4_7)	✅	Pin 7 is unconnected, which is acceptable as this pin is typically a key position or optional nTRST signal.
9	9	GND	✅	Ground pin correctly connected to GND net.
10	10	RESET	✅	nRESET pin connected to RESET net with reset button and capacitor. The RESET net appears separate from the NRST net used elsewhere in the design, which may indicate these nets are connected on another schematic page or through external circuitry.

U12 - AT25SF161-SSHD-T ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPIFLASH_CS	✅	CS# (Chip Select) is connected to SPIFLASH_CS with pull-up through diode OR-ing network. While the datasheet recommends a direct 10K pull-up, the indirect pull-up through D77 and R100 should be functionally adequate for the shared SPI bus design.
2	SO	MISO_M1BUS	✅	SO (Serial Output) is correctly connected to MISO_M1BUS, which is part of a shared SPI bus with tri-state buffer U16 to prevent bus conflicts.
3	WP#	WP#	✅	WP# (Write Protect) is correctly pulled high through R85 (10K to 3.3VCC), disabling write protection as intended.
4	GND	GND	✅	GND is correctly connected to the system ground plane.
5	SI/IO0	MOSI_M1BUS	✅	SI (Serial Input) is correctly connected to MOSI_M1BUS with appropriate 47R series resistor for signal integrity.
6	SCK	SCLK_M1BUS	✅	SCK (Serial Clock) is correctly connected to SCLK_M1BUS with appropriate 47R series resistor, clock buffering, and decoupling.
7	HOLD#	HOLD#	✅	HOLD# is connected to microcontroller GPIO PC30, allowing software control of the HOLD function or use as IO3 in quad-SPI mode. This is a valid design choice.
8	VCC	3.3VCC	✅	VCC is correctly connected to 3.3VCC with appropriate 100nF decoupling capacitor C164.

D77 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode is correctly connected to CS_M1BUS, which is part of the shared SPI bus chip select OR-ing logic with 10K pull-up R100.
K	K	SPIFLASH_CS	✅	Cathode is correctly connected to SPIFLASH_CS, allowing the SPI flash to be selected through either CS_M1BUS or directly by the microcontroller, and enabling proper MISO buffer control.

J18 - 0475710001 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	MCDA2	✅	DAT2 signal line correctly connected to MCDA2 on the microcontroller with appropriate ESD protection and pull-up resistor.
2	CD/DAT3	MCDA3	✅	CD/DAT3 signal line correctly connected to MCDA3 on the microcontroller with appropriate ESD protection and pull-up resistor.
3	CMD	MCCDA	✅	CMD signal line correctly connected to MCCDA on the microcontroller with appropriate ESD protection and pull-up resistor.
4	VDD	3.3VCC	✅	VDD power pin correctly connected to 3.3VCC with adequate decoupling capacitor.
5	CLK	MCCK	✅	CLK signal line correctly connected to MCCK on the microcontroller with appropriate ESD protection.
6	VSS	GND	✅	VSS ground pin correctly connected to GND.
7	DAT1	MCDA0	✅	DAT0 and DAT1 data lines are electrically connected correctly by pin number, but the schematic symbol has misleading pin labels showing them swapped.
8	DAT0	MCDA1	✅	DAT0 and DAT1 data lines are electrically connected correctly by pin number, but the schematic symbol has misleading pin labels showing them swapped.
9	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
10	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
11	SH	GND	✅	Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding.
12	CD	SDCD	✅	Card detect pin correctly connected to SDCD with pull-up resistor and ESD protection for active-low card presence detection.
13	CD/POL	GND	✅	Card detect polarity pin correctly connected to GND to set active-low polarity.

D42 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the SDCD signal line.
C	C	SDCD	✅	Cathode correctly connected to SDCD signal line for ESD protection on the card detect signal.

D64 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCDA1 signal line.
C	C	MCDA1	✅	Cathode correctly connected to MCDA1 signal line for ESD protection on SD card data line 1.

D65 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCDA0 signal line.
C	C	MCDA0	✅	Cathode correctly connected to MCDA0 signal line for ESD protection on SD card data line 0.

D66 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCCDA signal line.
C	C	MCCDA	✅	Cathode correctly connected to MCCDA signal line for ESD protection on SD card command line.

D67 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCCK signal line.
C	C	MCCK	✅	Cathode correctly connected to MCCK signal line for ESD protection on SD card clock line.

D68 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCDA3 signal line.
C	C	MCDA3	✅	Cathode correctly connected to MCDA3 signal line for ESD protection on SD card data line 3.

D69 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to GND for unidirectional ESD protection on the MCDA2 signal line.
C	C	MCDA2	✅	Cathode correctly connected to MCDA2 signal line for ESD protection on SD card data line 2.

J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external devices connected to this header.
2	2	GND	✅	Ground pin connected to GND net. Provides ground reference for external devices.
3	3	NetJ12_3	✅	Signal pin connected to PC2_PWML0 through 100R series resistor R137. Provides buffered PWM output signal.
4	4	NetJ12_4	✅	Signal pin connected to PA1_CANRX0 through 100R series resistor R136. Provides buffered CAN receive signal.
5	5	NetJ12_5	✅	Signal pin connected to PA16 through 100R series resistor R135. Provides buffered general purpose I/O signal.
6	6	NetJ12_6	✅	Signal pin connected to PA0_CANTX0 through 100R series resistor R134. Provides buffered CAN transmit signal.
7	7	NetJ12_7	✅	Signal pin connected to PA12_RXD1 through 100R series resistor R133. Provides buffered UART receive signal.
8	8	NetJ12_8	✅	Signal pin connected to PA15_CTS1 through 100R series resistor R120. Provides buffered UART clear-to-send signal.
9	9	NetJ12_9	✅	Signal pin connected to PA13_TXD1 through 100R series resistor R114. Provides buffered UART transmit signal.
10	10	NetJ12_10	✅	Signal pin connected to PA14_RTS1 through 100R series resistor R109. Provides buffered UART request-to-send signal.

J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VCC	✅	Power supply pin connected to +5VCC rail. Provides 5V power to external devices.
2	2	GND	✅	Ground pin connected to GND net. Provides ground reference.
3	3	NetJ13_3	✅	Signal pin connected to NRST through 100R series resistor R145. Provides buffered reset signal output.
4	4	NetJ13_4	✅	Signal pin connected to PB25_TIOA0 through 100R series resistor R144. Provides buffered timer I/O signal.
5	5	NetJ13_5	✅	Signal pin connected to PA26_MOSI through 100R series resistor R143. Provides buffered SPI MOSI signal.
6	6	NetJ13_6	✅	Signal pin connected to PA3_AD2 through 100R series resistor R142. Provides buffered ADC input signal.
7	7	NetJ13_7	✅	Signal pin connected to PA29_CS through 100R series resistor R141. Provides buffered SPI chip select signal.
8	8	NetJ13_8	✅	Signal pin connected to PB27_TIOB0 through 100R series resistor R140. Provides buffered timer I/O signal.
9	9	NetJ13_9	✅	Signal pin connected to PA27_SCLK through 100R series resistor R139. Provides buffered SPI clock signal.
10	10	NetJ13_10	✅	Signal pin connected to PA25_MISO through 100R series resistor R138. Provides buffered SPI MISO signal.

J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins connected to GND net. Provide ground reference for serial interface.
10	10	GND	✅	Ground pins connected to GND net. Provide ground reference for serial interface.
2	2	PA9_UTXD	✅	UART transmit signal connected directly to PA9_UTXD. Protected by ESD diode D72.
3	3	+5VCC	✅	5V power pins connected to +5VCC rail. Provide 5V power for external device.
8	8	+5VCC	✅	5V power pins connected to +5VCC rail. Provide 5V power for external device.
4	4	PA8_URXD	✅	UART receive signal connected directly to PA8_URXD. Protected by ESD diode D73.
5	5	3.3VCC	✅	3.3V power supply pin connected to 3.3VCC rail. Provides 3.3V power reference.
6	6	NRST	✅	Reset signal connected directly to NRST. Protected by ESD diode D71.
7	7	ERASE	✅	Erase signal connected directly to ERASE. Used for chip erase function.
9	9	PC8_PWML3	✅	PWM signal connected directly to PC8_PWML3. This signal lacks ESD protection, which is inconsistent with other signal pins on this connector, though it may be acceptable if used only as an output.

J20 - Header 12X2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PA28_CS0	✅	SPI chip select signal connected directly to PA28_CS0 from microcontroller.
2	2	PA27_SCLK	✅	SPI clock signal connected directly to PA27_SCLK from microcontroller.
3	3	PA26_MOSI	✅	SPI MOSI signal connected directly to PA26_MOSI from microcontroller.
4	4	PA25_MISO	✅	SPI MISO signal connected directly to PA25_MISO from microcontroller.
5	5	unconnected-(NetJ20_5)	✅	Unconnected pins. These pins are not used in the current design.
6	6	unconnected-(NetJ20_6)	✅	Unconnected pins. These pins are not used in the current design.
7	7	unconnected-(NetJ20_7)	✅	Unconnected pins. These pins are not used in the current design.
9	9	unconnected-(NetJ20_9)	✅	Unconnected pins. These pins are not used in the current design.
10	10	unconnected-(NetJ20_10)	✅	Unconnected pins. These pins are not used in the current design.
11	11	unconnected-(NetJ20_11)	✅	Unconnected pins. These pins are not used in the current design.
12	12	unconnected-(NetJ20_12)	✅	Unconnected pins. These pins are not used in the current design.
13	13	unconnected-(NetJ20_13)	✅	Unconnected pins. These pins are not used in the current design.
14	14	unconnected-(NetJ20_14)	✅	Unconnected pins. These pins are not used in the current design.
17	17	unconnected-(NetJ20_17)	✅	Unconnected pins. These pins are not used in the current design.
8	8	PB12_AD8	✅	ADC input signal connected directly to PB12_AD8 from microcontroller.
15	15	NetJ20_15	✅	Ethernet transmit data signal ETX0 connected through 100R resistor R161 and protected by varistor RV3.
16	16	NetJ20_16	✅	Ethernet transmit enable signal ETXEN connected through 100R resistor R160 and protected by varistor RV4.
18	18	NRST	✅	Reset signal connected directly to NRST. Allows external reset of the microcontroller.
19	19	NetJ20_19	✅	ADC input signal AD9 connected through 100R resistor R159 and protected by varistor RV2.
20	20	NetJ20_20	✅	Ethernet transmit clock signal ETXCK connected through 100R resistor R153 and protected by varistor RV1.
21	21	PA18_SCL	✅	I2C clock signal connected directly to PA18_SCL from microcontroller.
22	22	PA17_SDA	✅	I2C data signal connected directly to PA17_SDA from microcontroller.
23	23	GND	✅	Ground pin connected to GND net. Provides ground reference.
24	24	3.3VCC	✅	3.3V power supply pin connected to 3.3VCC rail. Provides 3.3V power.

D71 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND. Correct orientation for unidirectional ESD protection.
C	C	NRST	✅	Cathode connected to NRST signal. Provides ESD protection for the reset line exposed on external connectors.

D72 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND. Correct orientation for unidirectional ESD protection.
C	C	PA9_UTXD	✅	Cathode connected to PA9_UTXD signal. Provides ESD protection for the UART transmit line exposed on J28.

D73 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to GND. Correct orientation for unidirectional ESD protection.
C	C	PA8_URXD	✅	Cathode connected to PA8_URXD signal. Provides ESD protection for the UART receive line exposed on J28.

U14 - 74AVC9112 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	Vcc	3.3VCC	✅	VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C67 (100nF) nearby.
2	A	NetC64_2	✅	Input A correctly connected to PA27_SCLK from microcontroller through series resistor R82 (24R) and capacitor C64 for signal conditioning.
3	nOE	GND	✅	Output enable pin nOE correctly tied to GND to permanently enable all four outputs of the clock buffer.
4	GND	GND	✅	Ground pin correctly connected to GND.
5	Y1	NetR3_2	✅	Output Y1 correctly connected to SCLK_TCBUS through series resistor R3 (47R) for termination.
6	Y2	NetR4_2	✅	Output Y2 correctly connected to PA27_SCLK through series resistor R4 (47R) for termination.
7	Y3	NetR13_2	✅	Output Y3 correctly connected to SCLK_M1BUS through series resistor R13 (47R) for termination.
8	Y4	NetR32_2	✅	Output Y4 correctly connected to SCLK_M2BUS through series resistor R32 (47R) for termination.
23	NC		✅	No-connect pin, correctly left unconnected.

U16 - SN74LVC125A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	CS_TCBUS	✅	Output enable for buffer 1, correctly connected to CS_TCBUS to enable MISO_TCBUS when thermocouple bus is active.
2	A1	MISO_TCBUS	✅	Input A1 correctly connected to MISO_TCBUS from thermocouple bus devices.
3	Y1	NetR94_2	✅	Output Y1 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing.
4	nOE2	CS_M1BUS	✅	Output enable for buffer 2, correctly connected to CS_M1BUS to enable MISO_M1BUS when motor 1 bus is active.
5	A2	MISO_M1BUS	✅	Input A2 correctly connected to MISO_M1BUS from motor 1 bus devices including SPI flash.
6	Y2	NetR94_2	✅	Output Y2 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing.
7	GND	GND	✅	Ground pin correctly connected to GND.
8	Y3	NetR94_2	✅	Output Y3 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing.
9	A3	MISO_M2BUS	✅	Input A3 correctly connected to MISO_M2BUS from motor 2 bus devices.
10	nOE3	CS_M2BUS	✅	Output enable for buffer 3, correctly connected to CS_M2BUS to enable MISO_M2BUS when motor 2 bus is active.
11	Y4	unconnected-(NetU16_11)	✅	Output Y4 is unconnected but driven low since buffer 4 is enabled with input tied to GND. This is acceptable but buffer 4 could be disabled to save power.
12	A4	GND	✅	Input A4 correctly tied to GND since buffer 4 is unused.
13	nOE4	GND	✅	Output enable for buffer 4 tied to GND, enabling the unused buffer. Could be tied to VCC to disable and save power.
14	Vcc	3.3VCC	✅	VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C78 (100nF) nearby.
15	PAD	GND	✅	Thermal pad correctly connected to GND for heat dissipation.
23	NC		✅	No-connect pin, correctly left unconnected.

U17 - SN74LVC125A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	nOE1	GND	✅	Output enable for buffer 1 correctly tied to GND to permanently enable the buffer for MOSI fan-out.
2	A1	PA26_MOSI_D	✅	Input A1 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution.
3	Y1	NetR84_2	✅	Output Y1 correctly connected to MOSI_TCBUS through series resistor R84 (47R) for thermocouple bus.
4	nOE2	GND	✅	Output enable for buffer 2 correctly tied to GND to permanently enable the buffer for MOSI fan-out.
5	A2	PA26_MOSI_D	✅	Input A2 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution.
6	Y2	NetR59_2	✅	Output Y2 correctly connected to MOSI_M1BUS through series resistor R59 (47R) for motor 1 bus.
7	GND	GND	✅	Ground pin correctly connected to GND.
8	Y3	NetR89_2	✅	Output Y3 correctly connected to MOSI_M2BUS through series resistor R89 (47R) for motor 2 bus.
9	A3	PA26_MOSI_D	✅	Input A3 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution.
10	nOE3	GND	✅	Output enable for buffer 3 correctly tied to GND to permanently enable the buffer for MOSI fan-out.
11	Y4	NetR93_2	✅	Output Y4 correctly connected to PA26_MOSI through series resistor R93 (47R), possibly for local MOSI distribution.
12	A4	PA26_MOSI_D	✅	Input A4 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution.
13	nOE4	GND	✅	Output enable for buffer 4 correctly tied to GND to permanently enable the buffer for MOSI fan-out.
14	Vcc	3.3VCC	✅	VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C91 (100nF) nearby.
15	PAD	GND	✅	Thermal pad correctly connected to GND for heat dissipation.
23	NC		✅	No-connect pin, correctly left unconnected.

D41 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS7 is active.
K	K	M_nCS7	✅	Cathode correctly connected to M_nCS7 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D40 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS6 is active.
K	K	M_nCS6	✅	Cathode correctly connected to M_nCS6 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D63 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS8 is active.
K	K	M_nCS8	✅	Cathode correctly connected to M_nCS8 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D60 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M2BUS	✅	Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS5 is active.
K	K	M_nCS5	✅	Cathode correctly connected to M_nCS5 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D70 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS1 is active.
K	K	M_nCS1	✅	Cathode correctly connected to M_nCS1 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D74 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS2 is active.
K	K	M_nCS2	✅	Cathode correctly connected to M_nCS2 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D75 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS3 is active.
K	K	M_nCS3	✅	Cathode correctly connected to M_nCS3 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D76 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_M1BUS	✅	Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS4 is active.
K	K	M_nCS4	✅	Cathode correctly connected to M_nCS4 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D62 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS5 is active.
K	K	TC_nCS5	✅	Cathode correctly connected to TC_nCS5 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D5 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS4 is active.
K	K	TC_nCS4	✅	Cathode correctly connected to TC_nCS4 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D30 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS2 is active.
K	K	TC_nCS2	✅	Cathode correctly connected to TC_nCS2 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D31 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS3 is active.
K	K	TC_nCS3	✅	Cathode correctly connected to TC_nCS3 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

D61 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	CS_TCBUS	✅	Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS1 is active.
K	K	TC_nCS1	✅	Cathode correctly connected to TC_nCS1 microcontroller output to form wired-OR gate for automatic MISO buffer enable.

S1 - 1571610-2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	RESET	✅	Pin 1 (P) connects to the RESET net, which is the active-low reset signal for the JTAG interface. When the button is pressed, it connects to pins 2/3/4 (all at GND), pulling RESET low to assert the reset function.
2	S	GND	✅	Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function.
3	3	GND	✅	Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function.
4	4	GND	✅	Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function.

S2 - KMR741NG ULC LFS ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Net	Correct?	Analysis
1	3.3VCC	✅	Pin 1 connects to 3.3VCC. When the button is pressed, this pin connects to pin 3, pulling the ERASE signal high to 3.3V to assert the erase function.
2	unconnected-(NetS2_2)	✅	Pin 2 is marked as unconnected. This is acceptable for this switch type where only one terminal from each side needs to be connected, as pins 1 and 2 are typically internally connected in the switch.
3	ERASE	✅	Pin 3 connects to the ERASE net. When the button is pressed, this pin connects to pin 1 (3.3VCC), pulling ERASE high to assert the chip erase function on the microcontroller.
4	unconnected-(NetS2_4)	✅	Pin 4 is marked as unconnected. This is acceptable for this switch type where only one terminal from each side needs to be connected, as pins 3 and 4 are typically internally connected in the switch.

D1 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is connected to GND. This is the reference terminal for the ESD protection diode, providing the return path for ESD current.
C	C	ERASE	✅	Cathode is connected to the ERASE signal. This provides ESD protection for the ERASE net against both negative transients (via forward conduction) and excessive positive transients (via breakdown conduction).

D24 - 5988110107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD24_A	✅	Anode is correctly connected through a 1k current-limiting resistor (R34) to microcontroller GPIO pin PC3 (LED_R signal), allowing the MCU to control the red LED by sourcing current when the GPIO is driven high.
C	C	GND	✅	Cathode is correctly connected to ground, establishing a common-cathode LED configuration.

D25 - 5988140107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD25_A	✅	Anode is correctly connected through a 1k current-limiting resistor (R36) to microcontroller GPIO pin PC1 (LED_Y signal), allowing the MCU to control the yellow LED by sourcing current when the GPIO is driven high.
C	C	GND	✅	Cathode is correctly connected to ground, establishing a common-cathode LED configuration.

D44 - ESD9X3.3ST5G ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to GND for ESD protection of the 3.3VCC power rail.
K	K	3.3VCC	✅	Cathode is correctly connected to 3.3VCC power rail for ESD protection.

D45 - DF2S6.8FS,L3M ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to GND for ESD protection of the +5VCC power rail.
K	K	+5VCC	✅	Cathode is correctly connected to +5VCC power rail for ESD protection.

RV1 - AVRM0603C6R8NT101N ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_20	✅	Pin 1 is correctly connected to NetJ20_20, which connects through series resistor R153 (100R) to the PB0_ETXCK Ethernet signal for ESD protection.
2	2	GND	✅	Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages.

RV2 - AVRM0603C6R8NT101N ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_19	✅	Pin 1 is correctly connected to NetJ20_19, which connects through series resistor R159 (100R) to the PB13_AD9 ADC signal for ESD protection.
2	2	GND	✅	Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages.

RV3 - AVRM0603C6R8NT101N ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_15	✅	Pin 1 is correctly connected to NetJ20_15, which connects through series resistor R161 (100R) to the PB2_ETX0 Ethernet signal for ESD protection.
2	2	GND	✅	Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages.

RV4 - AVRM0603C6R8NT101N ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ20_16	✅	Pin 1 is correctly connected to NetJ20_16, which connects through series resistor R160 (100R) to the PB1_ETXEN Ethernet signal for ESD protection.
2	2	GND	✅	Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages.

J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC154_2	✅	Connected to the switched ground output from Q12A drain (NetC154_2), providing PWM-controlled ground connection to the fan motor.
2	S	VFAN	✅	Connected to VFAN power supply, providing positive power voltage to the fan motor.
3	S	NetJ29_3	✅	Connected to the tachometer signal from the fan through signal conditioning circuitry including pull-up resistor and voltage clamping protection.

Q12A - NCV8402AD ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source pin correctly connected to ground for low-side switching configuration.
2	G	NetQ12_2	✅	Gate pin driven through 100Ω resistor from tri-state buffer output, providing proper gate drive with current limiting and EMI reduction.
7	D	NetC154_2	✅	Drain pin connected to fan connector and indicator LED, providing switched ground output for PWM control.

LED1 - 5988110107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED1_A	✅	Anode connected through current-limiting resistor R96 (4.7kΩ) to VFAN, providing approximately 2.1mA LED current for status indication.
C	C	NetC154_2	✅	Cathode connected to switched output NetC154_2, causing LED to illuminate when MOSFET Q12A is conducting.

D50 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD50_A	✅	Anode connected to the tachometer signal node NetD50_A, forming upper clamp to prevent signal from exceeding 3.3V plus diode forward voltage.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC, providing overvoltage protection for tachometer signal by clamping to 3.3V rail.

D52 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode connected to ground, forming lower clamp to prevent tachometer signal from going below ground minus diode forward voltage.
K	K	NetD50_A	✅	Cathode connected to tachometer signal node NetD50_A, providing negative voltage protection.

U2D - SN74AHCT125 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
11	4Y	NetR98_1	✅	Output pin 4Y driving the gate of Q12A through 100Ω resistor, providing buffered PWM signal with adequate drive strength.
12	4A	FAN1	✅	Input pin 4A receiving FAN1 control signal with 10kΩ pull-down resistor ensuring defined logic low state when not actively driven.
13	4OE	GND	✅	Output enable pin 4OE tied to ground, permanently enabling the output to allow the input signal to pass through.

C155 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_1	✅	Filter capacitor on TACH_1 signal to ground, reducing high-frequency noise on tachometer input.
2	2	GND	✅	Filter capacitor on TACH_1 signal to ground, reducing high-frequency noise on tachometer input.

C154 - C0603TBD ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	Optional output filter capacitor marked DNI, would filter PWM noise between VFAN and switched output if installed.
2	2	NetC154_2	✅	Optional output filter capacitor marked DNI, would filter PWM noise between VFAN and switched output if installed.

TP8 - TestPoint ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
TP	TP	NetC154_2	✅	Test point on the switched fan output NetC154_2 for measurement and debugging.

R98 - RES 100R 0402 1% ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR98_1	✅	Gate resistor limiting current and reducing ringing on MOSFET gate drive between buffer output and Q12A gate.
2	2	NetQ12_2	✅	Gate resistor limiting current and reducing ringing on MOSFET gate drive between buffer output and Q12A gate.

R174 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_1	✅	Series resistor providing current limiting and isolation for tachometer input signal between TACH_1 and clamping network.
2	2	NetD50_A	✅	Series resistor providing current limiting and isolation for tachometer input signal between TACH_1 and clamping network.

R175 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD50_A	✅	Series resistor providing current limiting and isolation for tachometer output between clamping network and connector.
2	2	NetJ29_3	✅	Series resistor providing current limiting and isolation for tachometer output between clamping network and connector.

R172 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ29_3	✅	Pull-up resistor for open-collector tachometer signal, pulling NetJ29_3 to 3.3V logic level.
2	2	3.3VCC	✅	Pull-up resistor for open-collector tachometer signal, pulling NetJ29_3 to 3.3V logic level.

R96 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED1_A	✅	Current-limiting resistor for LED1, providing approximately 2.1mA at 12V supply between VFAN and LED anode.
2	2	VFAN	✅	Current-limiting resistor for LED1, providing approximately 2.1mA at 12V supply between VFAN and LED anode.

R183 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FAN1	✅	Pull-down resistor ensuring FAN1 control signal defaults to logic low when not driven, keeping fan off by default.
2	2	GND	✅	Pull-down resistor ensuring FAN1 control signal defaults to logic low when not driven, keeping fan off by default.

J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC153_2	✅	Fan negative terminal, connected to the drain of low-side switch Q12B through NetC153_2. This pin switches the fan ground return.
2	S	VFAN	✅	Fan positive supply terminal, connected to VFAN power rail. This provides the positive supply voltage to the fan.
3	S	NetJ22_3	✅	Fan tachometer signal input, connected through signal conditioning network including pull-up resistor R173 and series resistors R177/R176 with clamping diodes.

Q12B - NCV8402AD ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
3	S	GND	✅	Source terminal connected to GND. Correctly configured for low-side driver operation.
4	G	NetQ12_4	✅	Gate terminal driven by buffer U2C through 100Ω gate resistor R99. Correctly configured with appropriate gate drive.
5	D	NetC153_2	✅	Drain terminal switching the fan load. Correctly connected to fan connector and status LED.

U2C - SN74AHCT125 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
8	3Y	NetR99_1	✅	Output pin 3Y driving gate resistor R99, buffering the FAN2 control signal to drive the MOSFET gate.
9	3A	FAN2	✅	Input pin 3A receiving FAN2 control signal, which is pulled down to GND through R182.
10	3OE	GND	✅	Output enable pin 3OE tied to GND, keeping the buffer permanently enabled.

LED2 - 5988110107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED2_A	✅	Anode connected to VFAN through current limiting resistor R12 (4.7kΩ), providing proper current limiting for the indicator LED.
C	C	NetC153_2	✅	Cathode connected to the switched output NetC153_2, so the LED illuminates when Q12B is turned on.

D51 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD51_A	✅	Anode connected to NetD51_A in the tachometer signal conditioning circuit, forming part of the voltage divider and clamping network.
K	K	3.3VCC	✅	Cathode connected to 3.3VCC, providing positive voltage clamping for the tachometer signal to prevent overvoltage.

D53 - BAT54WX ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	unconnected-(NetD53_A)	❌	Anode is unconnected (floating), which is incorrect. This pin should be connected to GND to provide negative voltage clamping for the tachometer signal, matching the configuration of D52, D56, and D57 in the other three fan channels. Pin A is the anode terminal of the Schottky diode (from datasheet BAT54WX-TP, page 1) Pin A is connected to net unconnected-(NetD53_A), indicating it is floating (from schematic) In the parallel channel 1 circuit, D52 has its anode connected to GND and cathode to NetD50_A (from schematic) In channel 3, D56 has its anode connected to GND and cathode to NetD54_A (from schematic) In channel 4, D57 has its anode connected to GND and cathode to NetD55_A (from schematic) D51 and D53 should form a dual-diode clamp circuit for channel 2, with D51 clamping to 3.3VCC and D53 clamping to GND (reasoning) The purpose of this diode is to clamp negative-going voltages on the tachometer signal to ground, protecting downstream circuitry (reasoning) With the anode floating, D53 cannot perform its clamping function and the circuit lacks protection against negative voltage transients (reasoning) The anode of D53 should be connected to GND to match the design pattern of the other three identical tachometer circuits (reasoning)
K	K	NetD51_A	✅	Cathode connected to NetD51_A, which is correct for the lower clamping diode in the tachometer signal conditioning circuit. However, the diode cannot function properly without the anode connected to GND.

C156 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_2	✅	Connected to TACH_2 signal, providing filtering for the tachometer input.
2	2	GND	✅	Connected to GND, completing the filter capacitor configuration.

C153 - C0603TBD ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	Connected to VFAN power rail. This is an optional DNI capacitor for additional filtering.
2	2	NetC153_2	✅	Connected to NetC153_2, the switched output node.

TP1 - TestPoint ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
TP	TP	VFAN	✅	Test point connected to VFAN for voltage measurement.

TP2 - TestPoint ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
TP	TP	NetC153_2	✅	Test point connected to NetC153_2 for measuring the switched output.

R99 - RES 100R 0402 1% ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR99_1	✅	Connected to U2C output pin 8 (3Y) through NetR99_1.
2	2	NetQ12_4	✅	Connected to Q12B gate pin 4 through NetQ12_4, providing gate drive current limiting.

R176 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_2	✅	Connected to TACH_2 signal, part of the tachometer signal conditioning network.
2	2	NetD51_A	✅	Connected to NetD51_A, the intermediate node with clamping diodes.

R177 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD51_A	✅	Connected to NetD51_A, the intermediate node with clamping diodes.
2	2	NetJ22_3	✅	Connected to NetJ22_3, the tachometer input from the fan connector.

R173 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ22_3	✅	Connected to NetJ22_3, providing pull-up for the tachometer signal.
2	2	3.3VCC	✅	Connected to 3.3VCC, providing the pull-up voltage reference.

R12 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED2_A	✅	Connected to LED2 anode through NetLED2_A, providing current limiting for the indicator LED.
2	2	VFAN	✅	Connected to VFAN, providing the supply voltage for the LED circuit.

R182 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FAN2	✅	Connected to FAN2 control signal, providing pull-down to ensure defined logic state.
2	2	GND	✅	Connected to GND, providing the pull-down reference.

J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	NetC211_2	✅	Connected to the switched fan ground through the low-side MOSFET Q13A drain, providing the ground return path for the fan when Q13A is enabled.
2	S	VFAN	✅	Connected to VFAN power supply, providing the positive voltage to power the fan.
3	S	NetJ31_3	✅	Connected to the fan tachometer signal conditioning circuit through NetJ31_3, receiving the tachometer output from the fan.

Q13A - NCV8402AD ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	GND	✅	Source pin correctly connected to ground for low-side switch operation.
2	G	NetQ13_2	✅	Gate pin correctly driven through 100Ω resistor R180 from buffer U2B output for controlled MOSFET switching.
7	D	NetC211_2	✅	Drain pin correctly connected to fan load and LED indicator through connector J31.

U2B - SN74AHCT125 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
4	2OE	GND	✅	Output enable pin correctly tied to ground to permanently enable the buffer output.
5	2A	Fan3	✅	Input pin correctly connected to Fan3 control signal with 10kΩ pull-down resistor R171.
6	2Y	NetR180_1	✅	Output pin correctly drives MOSFET gate through 100Ω series resistor R180.

LED3 - 5988110107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED3_A	✅	Anode correctly connected through 4.7kΩ current limiting resistor R15 to VFAN supply.
C	C	NetC211_2	✅	Cathode correctly connected to switched output, allowing LED to indicate when fan is active.

D54 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD54_A	✅	Anode correctly connected to midpoint of tachometer voltage divider for signal conditioning.
K	K	3.3VCC	✅	Cathode correctly connected to 3.3VCC to clamp tachometer signal high.

D56 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode correctly connected to ground to clamp tachometer signal low.
K	K	NetD54_A	✅	Cathode correctly connected to midpoint of tachometer voltage divider, forming bidirectional clamp with D54.

C212 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_3	✅	Connected to TACH_3 signal for filtering tachometer input noise.
2	2	GND	✅	Connected to ground to complete the filter capacitor.

C211 - C0603TBD ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	Connected to VFAN supply for optional snubber/filter capacitor across fan load (marked DNI).
2	2	NetC211_2	✅	Connected to switched fan ground for optional snubber/filter capacitor (marked DNI).

TP18 - TestPoint ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
TP	TP	NetC211_2	✅	Test point connected to NetC211_2 for probing the switched fan ground output.

R180 - RES 100R 0402 1% ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR180_1	✅	Connected to buffer output U2B pin 6 for gate drive.
2	2	NetQ13_2	✅	Connected to MOSFET gate Q13A pin 2 for controlled switching.

R186 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_3	✅	Connected to TACH_3 input signal from tachometer.
2	2	NetD54_A	✅	Connected to midpoint of voltage divider and bidirectional clamp circuit.

R187 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD54_A	✅	Connected to midpoint of voltage divider and bidirectional clamp circuit.
2	2	NetJ31_3	✅	Connected to fan connector tachometer pin through NetJ31_3.

R184 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ31_3	✅	Connected to fan connector tachometer pin through NetJ31_3.
2	2	3.3VCC	✅	Connected to 3.3VCC to provide pull-up for tachometer signal.

R15 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED3_A	✅	Connected to LED3 anode for current limiting.
2	2	VFAN	✅	Connected to VFAN supply to provide current for LED indicator.

R171 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	Fan3	✅	Connected to Fan3 control signal input.
2	2	GND	✅	Connected to ground to provide pull-down for Fan3 control signal.

J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S	VFAN	✅	Pin 1 is connected to VFAN but should be connected to the switched output from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN.
2	S	VFAN	✅	Pin 2 is correctly connected to VFAN to provide unswitched power supply to the fan.
3	S	NetJ30_3	✅	Pin 3 is correctly connected to the tachometer signal conditioning circuit through NetJ30_3.

Q13B - NCV8402AD ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
5	D	VFAN	❌	Drain pin is incorrectly connected directly to VFAN instead of to a switched output node. This is the root cause preventing the fan control circuit from functioning. The drain should connect to a switched node that includes J30 pin 1, LED4 cathode, and C209 pin 2. Pin 5 is a Drain 2 terminal for channel 2 (from datasheet NCV8402ADDR2G, page 1) Pin 5 is connected to net VFAN (from schematic) In a low-side switching configuration, the drain should connect to the load being switched (from datasheet NCV8402ADDR2G, page 9) When the MOSFET turns on, it creates a low-resistance path from drain to source (ground) (from datasheet NCV8402ADDR2G) With the drain connected directly to VFAN, turning on the MOSFET would short VFAN directly to ground, which is incorrect (reasoning) Comparing to Q12B (channel 2 of Q12), its drain pin 5 connects to NetC153_2 which goes to J22 pin 1 and LED2 cathode (from schematic) Comparing to Q12A (channel 1 of Q12), its drain pin 7 connects to NetC154_2 which goes to J29 pin 1 and LED1 cathode (from schematic) Comparing to Q13A (channel 1 of Q13), its drain pin 7 connects to NetC211_2 which goes to J31 pin 1 and LED3 cathode (from schematic) Pin 5 should be connected to a switched output node (e.g., NetC209_2) that also connects to J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning) The current connection prevents the circuit from switching the fan power and would cause excessive current when the MOSFET turns on (reasoning) The NCV8402AD has current limit protection that would likely activate, but this is still an incorrect and potentially damaging configuration (from datasheet NCV8402ADDR2G, page 2)
3	S	GND	✅	Source pin is correctly connected to GND for low-side switching operation.
4	G	NetQ13_4	✅	Gate pin is correctly connected through a 100 ohm gate resistor (R181) to the buffer output (U2A pin 3).

LED4 - 5988110107F ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetLED4_A	✅	Anode is correctly connected through current limiting resistor R14 (4.7K) to VFAN.
C	C	VFAN	✅	Cathode is connected to VFAN but should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN.

D55 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	NetD55_A	✅	Anode is correctly connected to NetD55_A as part of the upper voltage clamp for the TACH_4 signal.
K	K	3.3VCC	✅	Cathode is correctly connected to 3.3VCC to clamp the tachometer signal to a safe voltage level.

D57 - BAT54WX ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	A	GND	✅	Anode is correctly connected to GND to provide lower voltage clamping for the TACH_4 signal.
K	K	NetD55_A	✅	Cathode is correctly connected to NetD55_A to complete the lower clamp circuit for the tachometer signal.

U2A - SN74AHCT125 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1OE	GND	✅	Output enable pin is correctly tied to GND to permanently enable the buffer output.
2	1A	Fan4	✅	Input pin is correctly connected to the Fan4 control signal.
3	1Y	NetR181_1	✅	Output pin is correctly connected through gate resistor R181 (100R) to drive the MOSFET gate of Q13B.

C213 - GRM155R71C104KA88D ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_4	✅	Pin 1 is correctly connected to TACH_4 signal for filtering.
2	2	GND	✅	Pin 2 is correctly connected to GND to complete the filter capacitor.

C209 - C0603TBD ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VFAN	✅	Both pins are connected to VFAN, but pin 2 should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. However, since this component is marked DNI (Do Not Install), the incorrect connection has no functional impact on the circuit.
2	2	VFAN	✅	Both pins are connected to VFAN, but pin 2 should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. However, since this component is marked DNI (Do Not Install), the incorrect connection has no functional impact on the circuit.

TP17 - TestPoint ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
TP	TP	VFAN	✅	Test point is correctly connected to VFAN for voltage measurement.

R181 - RES 100R 0402 1% ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetR181_1	✅	Pin 1 is correctly connected to the buffer output (U2A pin 3) to provide gate drive to Q13B.
2	2	NetQ13_4	✅	Pin 2 is correctly connected to the gate of Q13B (pin 4) to drive the MOSFET.

R188 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TACH_4	✅	Pin 1 is correctly connected to TACH_4 signal as part of the tachometer input circuit.
2	2	NetD55_A	✅	Pin 2 is correctly connected to NetD55_A, forming part of the tachometer signal conditioning network.

R189 - RC0402FR-071KL ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetD55_A	✅	Pin 1 is correctly connected to NetD55_A as part of the tachometer signal conditioning circuit.
2	2	NetJ30_3	✅	Pin 2 is correctly connected to NetJ30_3, which connects to the tachometer pin of the fan connector.

R185 - RC0402FR-071K8L ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetJ30_3	✅	Pin 1 is correctly connected to NetJ30_3, providing a pull-up for the tachometer signal.
2	2	3.3VCC	✅	Pin 2 is correctly connected to 3.3VCC to provide the pull-up voltage for the tachometer signal.

R14 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	NetLED4_A	✅	Pin 1 is correctly connected to the LED4 anode to provide current limiting.
2	2	VFAN	✅	Pin 2 is correctly connected to VFAN to provide the supply voltage for the LED circuit.

R101 - 10k 1% 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	Fan4	✅	Pin 1 is correctly connected to the Fan4 control signal to provide a pull-down.
2	2	GND	✅	Pin 2 is correctly connected to GND to complete the pull-down resistor.

U2E - SN74AHCT125 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
7	GND	GND	✅	Ground pin correctly connected to GND net.
14	VCC	+5VCC	✅	VCC pin correctly connected to +5VCC with appropriate bypass capacitor C92.
15	PAD	SNTP1	✅	Thermal pad (PAD) is connected to SNTP1 net instead of GND. While thermal pads are typically grounded for proper heat dissipation, the presence of a deliberate text label 'SNTP1' at coordinates (110.49, 34.29) near the component suggests this connection may be intentional for testing or measurement purposes. This should be verified to ensure SNTP1 is either connected to GND elsewhere in the design or serves a specific intended function.

C92 - 100nF 0402 16V X7R ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor pin correctly connected to GND for bypass capacitor function.
2	2	+5VCC	✅	Capacitor pin correctly connected to +5VCC, serving as bypass capacitor for U2E.

C106 - 100nF 6.3V X5R 0201 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Capacitor pin correctly connected to GND for bypass capacitor function.
2	2	3.3VCC	✅	Capacitor pin correctly connected to 3.3VCC, serving as bypass capacitor for the 3.3V rail.

📤 Upload Missing Datasheets

DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.

S1 (1571610-2): 📤 Upload a datasheet
P1 (2213S-08G): 📤 Upload a datasheet
J20 (2213S-24G): 📤 Upload a datasheet
C153, C154, C209, C211 (DNI-C0603TBD): 📤 Upload a datasheet
JP1, JP2 (NOTAPART-Solder Bridge): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 4 page(s) that changed in this DR. From these pages, DRCY selected 169 component(s) to review, and found 8 potential issue(s) in 13 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. > [!WARNING] > At least one netlist for this review was generated from a PCB layout file. If > the PCB is out of sync with the schematic, the analysis may be inaccurate. > Please ensure your PCB is up to date before relying on these results. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary>U1 - TPS54531 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftps54531) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | VIN | VPWR | ❌ | <details><summary>VIN pin connected to VPWR rail with inadequate input decoupling capacitance. Datasheet recommends 10µF ceramic capacitor close to VIN pin, but only 10nF (C71) is nearby with bulk capacitance far away.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="50.79,50.99,58.29,58.49" aspect-ratio="1.29" } <ul><li>Pin 2 (VIN) is connected to net VPWR (from schematic)</li><li>VPWR is the main input power rail derived from VPWR_IN through fuse F2 (from schematic)</li><li>C71 (10nF 0402 50V X7R) is the closest capacitor to U1 on the VPWR net (from schematic)</li><li>C199, C202, and C203 (each 100nF 0603) are connected to VPWR but located far from U1 (from schematic)</li><li>Total ceramic capacitance on VPWR near U1 is approximately 10nF from C71 plus 300nF from distant capacitors, totaling ~310nF (reasoning)</li><li>Datasheet specifies input voltage range of 3.5V to 28V (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=4">TPS54531DDAR</a>, page 4)</li><li>Datasheet requires input decoupling capacitor with typical recommended value of 10µF high-quality ceramic type X5R or X7R (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14">TPS54531DDAR</a>, page 14)</li><li>Datasheet design example uses two 4.7-µF capacitors for input decoupling, totaling 9.4µF (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=15">TPS54531DDAR</a>, page 15)</li><li>Datasheet layout guidelines state VIN pin must be bypassed to ground with low-ESR ceramic bypass capacitor with optimum placement closest to VIN pins (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=23">TPS54531DDAR</a>, page 23)</li><li>Datasheet emphasizes minimizing loop area formed by bypass capacitor connections, VIN pin, and anode of catch diode (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14">TPS54531DDAR</a>, page 14)</li><li>The total input capacitance of approximately 310nF is significantly less than the recommended 10µF (approximately 32× smaller) (reasoning)</li><li>Insufficient input decoupling capacitance can lead to increased input voltage ripple, potential instability, poor transient response, increased EMI, and potential damage to the IC (reasoning)</li><li>Recommendation: Add 10µF or greater ceramic capacitor (X5R or X7R) directly at U1 VIN pin with minimal loop area to meet datasheet requirements (reasoning)</li></ul></details> | | 1 | BOOT | NetC1_1 | ✅ | BOOT pin correctly connected to PH pin through 100nF bootstrap capacitor C1. | | 3 | EN | NetR2_2 | ✅ | EN pin correctly connected to UVLO voltage divider (R11/R2) and comparator outputs for enable control and undervoltage lockout. | | 4 | SS | NetC171_2 | ✅ | SS pin correctly connected to 10nF soft-start capacitor C171 to ground, matching datasheet example for 4ms soft-start time. | | 5 | VSNS | NetC3_1 | ✅ | VSNS pin correctly connected to output voltage feedback divider (R1/R5) for 5V output regulation. Sensing point is before current sense resistor R148, which causes output voltage to be slightly lower under load but is intentional for current monitoring. | | 6 | COMP | NetC150_2 | ✅ | COMP pin correctly connected to compensation network with R10 (37.4kΩ), C150 (2.2nF), and C151 (22pF), matching datasheet example values exactly. | | 7 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 8 | PH | NetC1_2 | ✅ | PH pin correctly connected to switching node with inductor L1, catch diode D2, and bootstrap capacitor C1. | | 9 | PAD | GND | ✅ | PowerPAD correctly connected to ground for thermal and electrical performance. | </details> <details> <summary>L1 - 4.7uH 10A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.bourns.com/docs/Product-Datasheets/SRP1038A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SRP1038A-4R7M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC1_2 | ✅ | Inductor input correctly connected to switching node (PH pin of U1) for buck converter operation. | | 2 | 2 | NetC3_2 | ✅ | Inductor output correctly connected to buck converter output node before current sense resistor R148. | </details> <details> <summary>D2 - SK54B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/SK52B-L_SK520B-L%28SMB%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SK54B-LTP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Catch diode correctly connected with anode to GND and cathode to switching node for freewheeling current path in buck converter. | | K | CATHODE | NetC1_2 | ✅ | Catch diode correctly connected with anode to GND and cathode to switching node for freewheeling current path in buck converter. | </details> <details> <summary>R148 - 0.01R 1% 0805 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.susumu.co.jp/common/pdf/n_catalog_partition09_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KRL1220E-M-R010-F-T5) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetC3_2 | ✅ | Current sense resistor correctly placed between buck converter output and +5VCC rail for current monitoring by U19. At 5A, voltage drop is 50mV and power dissipation is 0.25W, within the 0.5W rating. | | 2 | 2 | +5VCC | ✅ | Current sense resistor correctly placed between buck converter output and +5VCC rail for current monitoring by U19. At 5A, voltage drop is 50mV and power dissipation is 0.25W, within the 0.5W rating. | </details> <details> <summary>U8 - MIC5353-3.3YMT-TR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MIC5353-500mA-LDO-in-1.6mmx1.6mm-Package-DS20006507.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MIC5353-3.3YMT-TR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | EN | +5VCC | ✅ | EN pin is connected to +5VCC, configuring the regulator for always-on operation when input power is present. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net. | | 3 | VIN | +5VCC | ✅ | VIN pin is connected to +5VCC supply with proper input capacitor C34 (1µF X5R ceramic), which is within the specified operating range of 2.6V to 6V. | | 4 | VOUT | 3.3VCC | ✅ | VOUT pin provides 3.3V output to the 3.3VCC net with proper output capacitor C24 (1µF X5R ceramic), matching the fixed 3.3V output version specified by the part number. | | 5 | ADJ | unconnected-(NetU8_5) | ✅ | ADJ pin is correctly left unconnected, which is the proper configuration for the fixed voltage version of this regulator. | | 6 | BYP | NetC26_1 | ✅ | BYP pin is connected to a 100nF bypass capacitor (C26) to ground for reduced output noise and improved PSRR, matching the datasheet recommendation. | | 7 | PAD | GND | ✅ | PAD (exposed heatsink pad) is correctly connected to ground for proper thermal dissipation and electrical grounding. | </details> <details> <summary>U20 - 78L05 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.st.com/resource/en/datasheet/l78l.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/L78L05ABUTR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | OUT | 5V0_AUX | ✅ | OUT pin correctly provides regulated 5V output to the 5V0_AUX auxiliary power rail. Output is properly decoupled with two 100nF capacitors (C200, C201) providing 200nF total capacitance, which exceeds the minimum 0.1µF requirement specified in the datasheet. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the circuit ground reference as required by the datasheet. | | 3 | IN | VPWR | ✅ | IN pin is correctly connected to VPWR (12-24VDC input rail) which is within the 30V maximum input voltage specification. Input capacitance of approximately 0.3µF from three parallel 100nF capacitors (C199, C202, C203) is slightly below the recommended 0.33µF but within acceptable tolerance. These capacitors are shared with other circuits on VPWR rather than being dedicated to U20, though this should not significantly impact stability. | </details> <details> <summary>U19 - INA381_ALT ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fina381) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | CMPREF | NetR115_1 | ❌ | <details><summary>CMPREF pin connected to voltage divider formed by R115 (15kΩ) and R119 (4.7kΩ), but the resistor values are incorrect and set the current limit to approximately 2.4A instead of the intended ~4A per schematic text note. The voltage divider produces 1.193V instead of the required 2.0V for 4A threshold.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="51.70,29.24,59.20,36.74" aspect-ratio="1.29" } <ul><li>Pin 5 (CMPREF) is connected to net NetR115_1 (from schematic)</li><li>R115 (15kΩ) connects NetR115_1 to 5V0_AUX (from schematic)</li><li>R119 (4.7kΩ) connects NetR115_1 to GND (from schematic)</li><li>CMPREF is the input reference to the comparator per datasheet (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fina381#page=3">INA381A2IDSGR</a>, page 3)</li><li>Voltage divider produces VCMPREF = 5V × (4.7kΩ / 19.7kΩ) = 1.193V (reasoning)</li><li>INA381A2 has a gain of 50 V/V per datasheet (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fina381#page=5">INA381A2IDSGR</a>, page 5)</li><li>Current sense resistor R148 is 0.01Ω (10mΩ) (from schematic)</li><li>Current limit threshold = VCMPREF / (Gain × RSENSE) = 1.193V / (50 × 0.01Ω) = 2.386A (reasoning)</li><li>Schematic text note states 'Current Limiting for 5V rail (~4A)' (from schematic)</li><li>For 4A threshold: VCMPREF_needed = 4A × 0.01Ω × 50 = 2.0V (reasoning)</li><li>To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (reasoning)</li><li>Current resistor values result in approximately 60% of the intended current limit (2.4A vs 4A) (reasoning)</li><li>The incorrect threshold voltage is caused by wrong resistor values in R115 and R119 (reasoning)</li></ul></details> | | 1 | IN+ | NetC3_2 | ✅ | IN+ pin correctly connected to supply side of current sense resistor R148 on net NetC3_2 for high-side current sensing. | | 2 | Vs | 5V0_AUX | ✅ | Vs pin correctly powered from 5V0_AUX auxiliary supply with appropriate decoupling capacitor C201 (100nF). | | 3 | nALERT | NetR2_2 | ✅ | nALERT pin correctly configured as open-drain output with 10kΩ pull-up resistor R11 to VPWR, connected to buck converter enable pin for overcurrent shutdown. | | 4 | RESET | NetR102_1 | ✅ | RESET pin correctly pulled high through R102 (1kΩ) to 5V0_AUX to configure latching mode operation as intended. | | 6 | CMPIN | NetU19_6 | ✅ | CMPIN and VOUT pins correctly connected together on net NetU19_6, forming the standard configuration with default 50mV comparator hysteresis. | | 7 | VOUT | NetU19_6 | ✅ | CMPIN and VOUT pins correctly connected together on net NetU19_6, forming the standard configuration with default 50mV comparator hysteresis. | | 8 | IN- | +5VCC | ✅ | IN- pin correctly connected to load side of current sense resistor R148 on net +5VCC, completing the high-side current sensing configuration. | | 9 | GND | GND | ✅ | GND pin correctly connected to system ground net GND. | </details> <details> <summary>R102 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR102_1 | ✅ | 1kΩ pull-up resistor correctly configured between RESET pin (NetR102_1) and 5V0_AUX supply to enable latching mode operation of U19. | | 2 | 2 | 5V0_AUX | ✅ | 1kΩ pull-up resistor correctly configured between RESET pin (NetR102_1) and 5V0_AUX supply to enable latching mode operation of U19. | </details> <details> <summary>R115 - 15K 1% 0402 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F153CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR115_1 | ❌ | <details><summary>15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="40.80,33.35,48.30,40.85" aspect-ratio="1.29" } <ul><li>R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)</li><li>R115 pin 2 is connected to net 5V0_AUX (from schematic)</li><li>R115 value is 15kΩ per schematic (from schematic)</li><li>R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning)</li><li>Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)</li><li>Schematic text note indicates intended current limit is ~4A (from schematic)</li><li>For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)</li><li>To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)</li><li>With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)</li><li>Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)</li><li>The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)</li></ul></details> | | 2 | 2 | 5V0_AUX | ❌ | <details><summary>15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="40.80,32.18,48.30,39.68" aspect-ratio="1.29" } <ul><li>R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)</li><li>R115 pin 2 is connected to net 5V0_AUX (from schematic)</li><li>R115 value is 15kΩ per schematic (from schematic)</li><li>R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning)</li><li>Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)</li><li>Schematic text note indicates intended current limit is ~4A (from schematic)</li><li>For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)</li><li>To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)</li><li>With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)</li><li>Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)</li><li>The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)</li></ul></details> | </details> <details> <summary>R119 - 4.7k 1% 0402 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-074K7L) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="40.80,36.29,48.30,43.79" aspect-ratio="1.29" } <ul><li>R119 pin 1 is connected to net GND (from schematic)</li><li>R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)</li><li>R119 value is 4.7kΩ per schematic (from schematic)</li><li>R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold (reasoning)</li><li>Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)</li><li>Schematic text note indicates intended current limit is ~4A (from schematic)</li><li>For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)</li><li>To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)</li><li>With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)</li><li>Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)</li><li>The 4.7kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)</li></ul></details> | | 2 | 2 | NetR115_1 | ❌ | <details><summary>4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="40.80,35.12,48.30,42.62" aspect-ratio="1.29" } <ul><li>R119 pin 1 is connected to net GND (from schematic)</li><li>R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)</li><li>R119 value is 4.7kΩ per schematic (from schematic)</li><li>R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold (reasoning)</li><li>Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)</li><li>Schematic text note indicates intended current limit is ~4A (from schematic)</li><li>For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)</li><li>To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)</li><li>With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)</li><li>Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)</li><li>The 4.7kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)</li></ul></details> | </details> <details> <summary>D43 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to ground for uni-directional TVS protection of the VMOTA motor power rail. | | K | K | VMOTA | ✅ | Cathode is correctly connected to VMOTA motor power rail for transient voltage protection. | </details> <details> <summary>D22 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to ground for uni-directional TVS protection of the VPWR main power rail. | | K | K | VPWR | ✅ | Cathode is correctly connected to VPWR main power rail for transient voltage protection. | </details> <details> <summary>F1 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.keyelco.com/userAssets/file/K75p47.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-20) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBED_IN | ✅ | Input side of fuse holder, connected to VBED_IN from barrier connector J3 pin 7. This is the correct configuration for fuse input providing overcurrent protection for the heated bed power rail. | | 2 | 2 | VBED | ✅ | Output side of fuse holder, connected to VBED rail which supplies power to heated bed loads and protection circuitry. This is the correct configuration for fuse output. | </details> <details> <summary>D78 - SMAJ24A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode pin correctly connected to GND for uni-directional TVS protection of the VBED positive rail. This is the proper configuration for transient voltage suppression. | | K | K | VBED | ✅ | Cathode pin correctly connected to VBED rail for transient voltage protection of the heatbed power supply. The 24V TVS rating is appropriate for the 12-24VDC input range. | </details> <details> <summary>F2 - 3557-2 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.keyelco.com/userAssets/file/K75p47.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/3557-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR_IN | ✅ | Input side of fuse, connected to VPWR_IN from main power input connector J3 pin 5, providing overcurrent protection for the VPWR rail. | | 2 | 2 | VPWR | ✅ | Output side of fuse, connected to VPWR rail which distributes power to the TPS54531 buck regulator, 78L05 LDO, comparators, and external loads through header P1. Protected by TVS diode D22 and filtered by multiple capacitors. | </details> <details> <summary>D21 - SMAJ24A ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | VMOTE | ❌ | <details><summary>The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="2.64,54.99,10.14,62.49" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic)</li><li>SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The cathode is marked with a color band in uni-directional configuration (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=3">SMAJ24A</a>, page 3)</li><li>During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning)</li><li>With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning)</li><li>All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic)</li><li>D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic)</li><li>D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic)</li><li>D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic)</li><li>The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning)</li><li>The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)</li></ul></details> | | K | K | GND | ❌ | <details><summary>The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="2.64,56.16,10.14,63.66" aspect-ratio="1.29" } <ul><li>Pin A (Anode) is connected to net VMOTE (from schematic)</li><li>Pin K (Cathode) is connected to net GND (from schematic)</li><li>VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic)</li><li>SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>The cathode is marked with a color band in uni-directional configuration (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1">SMAJ24A</a>, page 1)</li><li>For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet <a href="https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=3">SMAJ24A</a>, page 3)</li><li>During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning)</li><li>With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning)</li><li>All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic)</li><li>D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic)</li><li>D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic)</li><li>D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic)</li><li>The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning)</li><li>The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)</li></ul></details> | </details> <details> <summary>U21 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR157_1 | ✅ | IN- (inverting input) is correctly connected to a reference voltage divider formed by R157 (130k from 5V0_AUX) and R158 (100k to GND), providing approximately 2.17V reference voltage. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the ground reference for the comparator. | | 3 | IN+ | NetR154_2 | ✅ | IN+ (non-inverting input) is correctly connected to a voltage divider (R154/R155) that senses VMOTA, with hysteresis feedback through R156. | | 4 | OUT | NetR2_2 | ✅ | Output pin is correctly connected to NetR2_2 as an open-collector output with external pull-up resistor R11 (10k to VPWR) and pull-down R2 (1.4k to GND), forming a wired-OR enable signal. | | 5 | VCC | VPWR | ✅ | VCC pin is correctly connected to VPWR, providing power to the comparator within its specified operating range. | </details> <details> <summary>R154 - 24k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040224K0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOTA | ✅ | Connected to VMOTA, forming the top of the voltage divider that senses the motor supply voltage. | | 2 | 2 | NetR154_2 | ✅ | Connected to NetR154_2, the junction of the voltage divider and the IN+ input of U21. | </details> <details> <summary>R155 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the bottom of the voltage divider. | | 2 | 2 | NetR154_2 | ✅ | Connected to NetR154_2, the junction of the voltage divider and the IN+ input of U21. | </details> <details> <summary>R156 - 1M 5% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://industrial.panasonic.com/cdbs/www-data/pdf/RDA0000/AOA0000C301.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ERJ2GEJ105X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis. | | 2 | 2 | NetR154_2 | ✅ | Connected to NetR154_2 (IN+ of comparator), completing the hysteresis feedback path. | </details> <details> <summary>R157 - 130k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402JR-07130KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR157_1 | ✅ | Connected to NetR157_1, the junction of the reference voltage divider and the IN- input of U21. | | 2 | 2 | 5V0_AUX | ✅ | Connected to 5V0_AUX, forming the top of the reference voltage divider. Note: Part number RC0402JR-07130KL indicates 5% tolerance (J code), but component specifies 1% tolerance; correct part number should be RC0402FR-07130KL (F code). | </details> <details> <summary>R158 - 100k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the bottom of the reference voltage divider. | | 2 | 2 | NetR157_1 | ✅ | Connected to NetR157_1, the junction of the reference voltage divider and the IN- input of U21. | </details> <details> <summary>U6 - AP331A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP331A.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AP331AWG-7) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN- | NetR57_1 | ✅ | Inverting input (IN-) connected to a precision reference voltage divider from 5V0_AUX through R57 (130k) and R58 (100k), providing a stable threshold reference of approximately 2.175V. | | 2 | GND | GND | ✅ | Ground reference pin correctly connected to GND net. | | 3 | IN+ | NetR26_2 | ✅ | Non-inverting input (IN+) connected to a voltage divider monitoring VMOTE through R26 (24k) and R56 (10k), with positive feedback via R28 (1M) for hysteresis, creating an undervoltage detection circuit with threshold around 7.4V. | | 4 | OUT | NetR2_2 | ✅ | Open collector output correctly connected to NetR2_2 with external pull-up resistor R11 (10k to VPWR), wired-OR with U21 output to control enable signal for main power supply. | | 5 | VCC | VPWR | ✅ | Power supply pin (Vcc) correctly connected to VPWR, which is within the comparator's operating voltage range of 2-36V. | </details> <details> <summary>R26 - 24k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/28773/crcwce3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW040224K0FKEDC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOTE | ✅ | Connected to VMOTE, forming the upper leg of the voltage divider that monitors the motor supply voltage. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2, the midpoint of the voltage divider that feeds the non-inverting input of U6. | </details> <details> <summary>R56 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the lower leg of the voltage divider that monitors VMOTE. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2, the midpoint of the voltage divider that feeds the non-inverting input of U6. | </details> <details> <summary>R28 - 1M 5% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://industrial.panasonic.com/cdbs/www-data/pdf/RDA0000/AOA0000C301.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ERJ2GEJ105X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Connected to NetR2_2 (comparator output), providing positive feedback for hysteresis. | | 2 | 2 | NetR26_2 | ✅ | Connected to NetR26_2, providing positive feedback to the non-inverting input of U6 for hysteresis. | </details> <details> <summary>R57 - 130k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402JR-07130KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR57_1 | ✅ | Connected to NetR57_1, the midpoint of the reference voltage divider that feeds the inverting input of U6. | | 2 | 2 | 5V0_AUX | ✅ | Connected to 5V0_AUX, forming the upper leg of the reference voltage divider. | </details> <details> <summary>R58 - 100k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F104CS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the lower leg of the reference voltage divider. | | 2 | 2 | NetR57_1 | ✅ | Connected to NetR57_1, the midpoint of the reference voltage divider that feeds the inverting input of U6. | </details> <details> <summary>J3 - 10 Pos barrier ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/4DB-P108-10) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VMOTE | ❌ | <details><summary>Connected to VMOTE net, which powers motors 5-8. However, the TVS diode D21 protecting this rail is connected backwards (anode on VMOTE, cathode on GND), which will not provide proper overvoltage protection.</summary>!thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="2.64,36.29,10.14,43.79" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to the VMOTE net (from schematic)</li><li>VMOTE powers motors 5-8 based on nearby text annotation (from schematic)</li><li>VMOTE is protected by TVS diode D21 (SMAJ24A) (from schematic)</li><li>D21 has its anode (A) connected to VMOTE and cathode (K) connected to GND (from schematic)</li><li>For proper overvoltage protection, unidirectional TVS diodes should have cathode on the power rail and anode on ground to clamp positive voltage transients (reasoning)</li><li>All other TVS diodes on the board (D43 on VMOTA, D22 on VPWR, D78 on VBED) are correctly oriented with cathode on power rail and anode on ground (from schematic)</li><li>D21 is connected backwards compared to the other TVS diodes, which will prevent it from providing proper overvoltage protection and may conduct in normal operation (reasoning)</li><li>D21 should be reversed to have cathode on VMOTE and anode on GND (reasoning)</li><li>The barrier block is rated for 20A at 150V (UL Class C) and 10A at 300V (UL Class D), which is adequate for 12-24VDC motor power input (from datasheet <a href="https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English">4DB-P108-10</a>)</li><li>Wire range is 12-22 AWG, suitable for high current motor power connections (from datasheet <a href="https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English">4DB-P108-10</a>)</li></ul></details> | | 2 | 2 | GND | ✅ | Connected to GND. This provides a ground return path adjacent to the VMOTE power input on pin 1. | | 3 | 3 | VMOTA | ✅ | Connected to VMOTA net, which powers motors 1-4. The connection is correct and properly protected. | | 4 | 4 | GND | ✅ | Connected to GND. This provides a ground return path adjacent to the VMOTA power input on pin 3. | | 5 | 5 | VPWR_IN | ✅ | Connected to VPWR_IN net, which is the input for fans, expansion, heaters, and logic power. The connection is correct. | | 6 | 6 | GND | ✅ | Connected to GND. This provides a ground return path adjacent to the VPWR_IN power input on pin 5. | | 7 | 7 | VBED_IN | ✅ | Connected to VBED_IN net, which is the input for heated bed power. The connection is correct. | | 8 | 8 | GND | ✅ | Connected to GND. This provides a ground return path adjacent to the VBED_IN power input on pin 7. | | 9 | 9 | VBED | ✅ | Connected to VBED net, which is the fused heated bed power output. The connection is correct, though having both VBED_IN (pin 7) and VBED (pin 9) on the same connector is an unusual design choice. | | 10 | 10 | HTBD-OUT | ✅ | Connected to HTBD-OUT net, which appears to be a heated bed control output signal. The net only connects to this pin on the visible schematic page, suggesting it may connect to circuitry on another page or be an external output. | </details> <details> <summary>P1 - Header 4X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | Both pins connected to VFAN net, which provides fan power. VFAN is derived from VPWR through 0R jumper R103. | | 3 | 3 | VFAN | ✅ | Both pins connected to VFAN net, which provides fan power. VFAN is derived from VPWR through 0R jumper R103. | | 2 | 2 | GND | ✅ | Both pins connected to GND, providing ground return paths for the VFAN outputs on pins 1 and 3. | | 4 | 4 | GND | ✅ | Both pins connected to GND, providing ground return paths for the VFAN outputs on pins 1 and 3. | | 5 | 5 | VPWR | ✅ | Both pins connected to VPWR net, which provides main power for fans, expansion, heaters, and logic circuits. | | 7 | 7 | VPWR | ✅ | Both pins connected to VPWR net, which provides main power for fans, expansion, heaters, and logic circuits. | | 6 | 6 | GND | ✅ | Both pins connected to GND, providing ground return paths for the VPWR outputs on pins 5 and 7. | | 8 | 8 | GND | ✅ | Both pins connected to GND, providing ground return paths for the VPWR outputs on pins 5 and 7. | </details> <details> <summary>D23 - 5988170107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988170107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD23_A | ✅ | LED anode is correctly connected to 3.3VCC through current-limiting resistor R33 (1kΩ), forming a power indicator circuit for the 3.3V rail. | | C | C | GND | ✅ | LED cathode is correctly connected to GND, providing the return path for the indicator LED circuit. | </details> <details> <summary>R33 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD23_A | ✅ | Resistor terminal connects to LED D23 anode, providing current limiting for the power indicator LED. | | 2 | 2 | 3.3VCC | ✅ | Resistor terminal connects to 3.3VCC power rail, sourcing current for the LED indicator circuit. | </details> <details> <summary>R11 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_51_ROHS_P) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0710KP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR2_2 | ✅ | Connected to NetR2_2, forming the middle node of a voltage divider that provides enable voltage to U1 and allows comparator-based UVLO protection. | | 2 | 2 | VPWR | ✅ | Connected to VPWR, the main input power rail, forming the top of the enable voltage divider. | </details> <details> <summary>R2 - 1.4k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.seielect.com/catalog/SEI-RMCF_RMCP.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RMCF0402FT1K40) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, forming the bottom of the enable voltage divider. | | 2 | 2 | NetR2_2 | ✅ | Connected to NetR2_2, forming the middle node of the voltage divider that sets the enable voltage for U1. | </details> <details> <summary>R103 - 0R 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://bourns.com/docs/product-datasheets/cr.pdf?sfvrsn=574d41f6_14) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CR0603-J_-000ELF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VPWR | ✅ | Pin 1 connects to VPWR, the main power rail that supplies the buck regulator, comparators, and LDO. This is one terminal of the 0-ohm jumper. | | 2 | 2 | VFAN | ✅ | Pin 2 connects to VFAN, which supplies power to fan connectors on header P1. This is the other terminal of the 0-ohm jumper. | </details> <details> <summary>J8 - USB-B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.waldom.com/productfiles/mf-fci/61729.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/61729-0010BLF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS | NetC43_2 | ✅ | VBUS pin correctly connected to USB power input with ESD protection, filtering capacitor, and ferrite bead to VUSB supply. | | 2 | DM | DM | ✅ | D- data line correctly connected to ESD protection device for USB differential signaling. | | 3 | DP | DP | ✅ | D+ data line correctly connected to ESD protection device for USB differential signaling. | | 4 | GND | USB_GND | ✅ | Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology. | | 5 | SHLD | USB_GND | ✅ | Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology. | | 6 | SHLD | USB_GND | ✅ | Ground and shield pins correctly connected to isolated USB ground domain for proper USB isolation topology. | </details> <details> <summary>D27 - PRTR5V0U2F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2F_PRTR5V0U2K.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/PRTR5V0U2F,115) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | DM | ✅ | I/O1 pin correctly connected to USB D- data line from connector for ESD protection. | | 2 | | USB_GND | ✅ | Ground pin correctly connected to isolated USB ground domain. | | 3 | | DP | ✅ | I/O2 pin correctly connected to USB D+ data line from connector for ESD protection. | | 4 | | NetD27_4 | ✅ | I/O2 pin correctly connected through common mode choke to isolated USB interface. | | 5 | | NetC43_2 | ✅ | VCC pin correctly connected to USB VBUS for supply-referenced ESD protection. | | 6 | | NetD27_6 | ✅ | I/O1 pin correctly connected through common mode choke to isolated USB interface. | </details> <details> <summary>D26 - RSB39VTE-17 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://fscdn.rohm.com/en/products/databook/datasheet/discrete/diode/zener/rsb39v.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RSB39VTE-17) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Bidirectional TVS diode correctly placed between USB_GND and GND for isolation barrier overvoltage protection. | | C | C | USB_GND | ✅ | Bidirectional TVS diode correctly placed between USB_GND and GND for isolation barrier overvoltage protection. | </details> <details> <summary>L5 - DLW21HN900SQ2L ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/commonModeChokeCoilCommonModeNoiseFilter/EFLC0005_PDF_COMMONMODECHOKECOILCOMMONMODENOISEFILTER?lastModifiedDatetime=20250707191631) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DLW21HN900SQ2L) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | NetL5_1 | ✅ | Common mode choke output for D+ line, correctly connected through series resistor to USB isolator positive data input. | | 2 | | NetD27_4 | ✅ | Common mode choke input for D+ line, correctly connected to ESD protection device output. | | 3 | | NetD27_6 | ✅ | Common mode choke input for D- line, correctly connected to ESD protection device output. | | 4 | | NetL5_4 | ✅ | Common mode choke output for D- line, correctly connected through series resistor to USB isolator negative data input. | </details> <details> <summary>U9 - ADuM4160 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM3160.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ADUM3160BRWZ-RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUS1 | VUSB | ✅ | VBUS1 is correctly connected to VUSB, which provides 5V power from the USB bus through protection circuitry including ferrite bead FB29 and TVS diode D27. | | 2 | GND1 | USB_GND | ✅ | GND1 pins are correctly connected to USB_GND, providing isolated ground reference for the upstream side of the isolator. | | 8 | GND1 | USB_GND | ✅ | GND1 pins are correctly connected to USB_GND, providing isolated ground reference for the upstream side of the isolator. | | 3 | VDD1 | VDD1 | ✅ | VDD1 is correctly connected to the VDD1 net, which is the regulated 3.3V output from the internal LDO regulator with proper bypass capacitor. | | 4 | PDEN | VDD1 | ✅ | PDEN is correctly tied to VDD1 for standard operation, enabling normal downstream pull-down resistor operation. | | 5 | SPU | VDD1 | ✅ | SPU is correctly tied high to VDD1, selecting full speed operation for the upstream buffer and matching the SPD pin configuration. | | 6 | UD- 1 | UD_N | ✅ | UD- is correctly connected to the upstream USB D- line through series termination resistor R43 (24Ω) as required for full speed operation. | | 7 | UD+ 1 | UD_P | ✅ | UD+ is correctly connected to the upstream USB D+ line through series termination resistor R46 (24Ω) as required for full speed operation. | | 9 | GND2 | GND | ✅ | GND2 pins are correctly connected to system GND, providing isolated ground reference for the downstream side of the isolator. | | 15 | GND2 | GND | ✅ | GND2 pins are correctly connected to system GND, providing isolated ground reference for the downstream side of the isolator. | | 10 | UD+ 2 | UI_P | ✅ | DD+ (labeled UD+ 2 in schematic) is correctly connected to the downstream USB D+ line through series termination resistor R47 (24Ω) to the microcontroller. | | 11 | UD- 2 | UI_N | ✅ | DD- (labeled UD- 2 in schematic) is correctly connected to the downstream USB D- line through series termination resistor R45 (24Ω) to the microcontroller. | | 12 | PIN | 3.3VCC | ✅ | PIN is correctly connected to 3.3VCC, which enables the upstream pull-up resistor for USB enumeration. The net naming (3.3VCC vs +3.3VCC) suggests this may be intentional for delayed enumeration control, though both configurations are functionally acceptable. | | 13 | SPD | 3.3VCC | ✅ | SPD is correctly connected to 3.3VCC to select full speed operation for the downstream buffer, matching the SPU pin configuration. | | 14 | VDD2 | +3.3VCC | ✅ | VDD2 is correctly connected to +3.3VCC with proper bypass capacitors, providing 3.3V power supply for the downstream side of the isolator. | | 16 | VBUS2 | +3.3VCC | ✅ | VBUS2 is correctly connected to +3.3VCC along with VDD2, configuring the downstream side for 3.3V operation and bypassing the internal regulator. | </details> <details> <summary>R43 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_N | ✅ | Resistor terminal 1 is correctly connected to UD_N from the USB isolator upstream D- pin (U9 pin 6). | | 2 | 2 | NetL5_4 | ✅ | Resistor terminal 2 is correctly connected to NetL5_4, which goes to the common mode choke L5 and then to the USB connector D- line. | </details> <details> <summary>R46 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UD_P | ✅ | Resistor terminal 1 is correctly connected to UD_P from the USB isolator upstream D+ pin (U9 pin 7). | | 2 | 2 | NetL5_1 | ✅ | Resistor terminal 2 is correctly connected to NetL5_1, which goes to the common mode choke L5 and then to the USB connector D+ line. | </details> <details> <summary>R47 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_P | ✅ | Resistor terminal 1 is correctly connected to UMCU_P, which goes to the microcontroller USB D+ pin (U11B pin 37, DHSDP). | | 2 | 2 | UI_P | ✅ | Resistor terminal 2 is correctly connected to UI_P from the USB isolator downstream D+ pin (U9 pin 10). | </details> <details> <summary>R45 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | UMCU_N | ✅ | Resistor terminal 1 is correctly connected to UMCU_N, which goes to the microcontroller USB D- pin (U11B pin 38, DHSDM). | | 2 | 2 | UI_N | ✅ | Resistor terminal 2 is correctly connected to UI_N from the USB isolator downstream D- pin (U9 pin 11). | </details> <details> <summary>U11B - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 37 | DHSDP | UMCU_P | ❌ | <details><summary>The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="34.89,19.25,42.39,26.75" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic)</li><li>Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic)</li><li>Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic)</li><li>Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic)</li><li>UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic)</li><li>DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic)</li><li>The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=1401-1402">ATSAM3X8EA-AU</a>, page 1401-1402)</li><li>Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning)</li><li>The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning)</li><li>Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning)</li><li>Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning)</li><li>Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning)</li><li>Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)</li></ul></details> | | 38 | DHSDM | UMCU_N | ❌ | <details><summary>The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="34.89,22.77,42.39,30.27" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic)</li><li>Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic)</li><li>Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic)</li><li>Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic)</li><li>UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic)</li><li>DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic)</li><li>The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=1401-1402">ATSAM3X8EA-AU</a>, page 1401-1402)</li><li>Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning)</li><li>The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning)</li><li>Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning)</li><li>Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning)</li><li>Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning)</li><li>Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)</li></ul></details> | | 42 | DFSDP | NetR48_1 | ❌ | <details><summary>The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="34.89,20.42,42.39,27.92" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic)</li><li>Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic)</li><li>Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic)</li><li>Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic)</li><li>UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic)</li><li>DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic)</li><li>The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=1401-1402">ATSAM3X8EA-AU</a>, page 1401-1402)</li><li>Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning)</li><li>The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning)</li><li>Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning)</li><li>Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning)</li><li>Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning)</li><li>Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)</li></ul></details> | | 43 | DFSDM | NetR42_1 | ❌ | <details><summary>The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="34.89,23.95,42.39,31.45" aspect-ratio="1.29" } <ul><li>Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic)</li><li>Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic)</li><li>Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic)</li><li>Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic)</li><li>UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic)</li><li>DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic)</li><li>The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=1401-1402">ATSAM3X8EA-AU</a>, page 1401-1402)</li><li>Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning)</li><li>The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning)</li><li>Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning)</li><li>Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning)</li><li>Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning)</li><li>Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)</li></ul></details> | | 35 | XOUT | NetC41_2 | ✅ | XOUT is correctly connected to the 12MHz crystal oscillator output through a 3pF load capacitor. | | 36 | XIN | NetC42_2 | ✅ | XIN is correctly connected to the 12MHz crystal oscillator input through a 3pF load capacitor. | | 39 | VBUS | VBUS_UC | ✅ | VBUS is correctly connected to a USB bus power detection circuit that provides isolated sensing of USB power presence. | | 40 | VBG | NetC49_1 | ✅ | VBG is correctly connected with a 6.8kΩ ±1% resistor and 10pF capacitor to ground, exactly matching the datasheet specification. | | 46 | JTAGSEL | GND | ✅ | JTAGSEL is correctly connected to GND for normal JTAG operation mode. | | 47 | NRSTB | RESET | ✅ | NRSTB is correctly connected to the RESET net for asynchronous microcontroller reset. | | 48 | XIN32 | XIN32 | ✅ | XIN32 is correctly connected to the 32.768 kHz slow clock oscillator input. | | 49 | XOUT32 | XOUT32 | ✅ | XOUT32 is correctly connected to the 32.768 kHz slow clock oscillator output. | | 50 | SHDN | SHDN | ✅ | SHDN is correctly connected as an output pin indicating device shutdown state. | | 51 | TST | GND | ✅ | TST is correctly connected to GND for normal operation (not test mode). | | 53 | FWUP | NetR51_1 | ✅ | FWUP is correctly connected with a 100kΩ pull-up resistor to +3.3VCC as required by the datasheet. | | 69 | NRST | NetC169_1 | ✅ | NRST is correctly connected with a 100nF filter capacitor and 100Ω series resistor for reset signal conditioning. | | 75 | ADVREF | VDDANA | ✅ | ADVREF is correctly connected to VDDANA for ADC and DAC voltage reference. | </details> <details> <summary>R48 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR48_1 | ✅ | R48 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R48 should be removed or marked as DNI. | | 2 | 2 | UMCU_P | ✅ | R48 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R48 should be removed or marked as DNI. | </details> <details> <summary>R42 - CRCW040224R0FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-0724RL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR42_1 | ✅ | R42 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R42 should be removed or marked as DNI. | | 2 | 2 | UMCU_N | ✅ | R42 is a 24Ω series resistor that is part of the incorrect USB connection scheme. The fundamental issue is in U11B pins 37, 38, 42, 43 where both high-speed and full-speed USB interfaces are incorrectly connected together. R42 should be removed or marked as DNI. | </details> <details> <summary>U18 - OPTO SO-4 OPNDRN OUT ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://toshiba.semicon-storage.com/info/docget.jsp?did=14419&prodName=TLP293) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TLP293%28TPL,E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A | NetR152_2 | ✅ | Anode of optocoupler LED correctly connected to VUSB through 1kΩ current limiting resistor R152, providing approximately 3.75mA LED current for USB power detection. | | 2 | K | USB_GND | ✅ | Cathode of optocoupler LED correctly connected to USB_GND to complete the LED circuit on the isolated USB side. | | 3 | E | GND | ✅ | Emitter of phototransistor correctly connected to GND (system ground) to provide reference for the output side of the optocoupler. | | 4 | C | NetQ8_1 | ✅ | Collector of phototransistor correctly connected to Q8 base through net NetQ8_1 with 6.8kΩ pull-up resistor R151. When LED is on, phototransistor pulls base low to turn off Q8. | </details> <details> <summary>Q8 - MMBT3904_SOT523 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/ds30270.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/MMBT3904T-7-F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B | NetQ8_1 | ✅ | Base correctly connected to optocoupler collector output through net NetQ8_1 with 6.8kΩ pull-up resistor R151. Receives control signal from optocoupler to switch VBUS_UC. | | 2 | E | GND | ✅ | Emitter correctly connected to GND for standard common-emitter switch configuration. | | 3 | C | VBUS_UC | ✅ | Collector correctly connected to VBUS_UC with 6.8kΩ pull-up resistor R150. Pulls VBUS_UC low when transistor is on (no USB power), allows pull-up when off (USB power present). | </details> <details> <summary>R152 - RK73H1ETTP1001F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-071KL) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | 1kΩ current limiting resistor for optocoupler LED, correctly connected between VUSB and LED anode with appropriate value for approximately 3.75mA LED current. | | 2 | 2 | NetR152_2 | ✅ | 1kΩ current limiting resistor for optocoupler LED, correctly connected between VUSB and LED anode with appropriate value for approximately 3.75mA LED current. | </details> <details> <summary>R150 - CRCW04026K80FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VBUS_UC | ✅ | 6.8kΩ pull-up resistor for VBUS_UC signal, correctly connected between VBUS_UC and +5VCC with appropriate value. | | 2 | 2 | +5VCC | ✅ | 6.8kΩ pull-up resistor for VBUS_UC signal, correctly connected between VBUS_UC and +5VCC with appropriate value. | </details> <details> <summary>R151 - CRCW04026K80FKED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/20035/dcrcwe3.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CRCW04026K80FKED) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetQ8_1 | ✅ | 6.8kΩ pull-up resistor for Q8 base, correctly connected between Q8 base and +5VCC with appropriate value. | | 2 | 2 | +5VCC | ✅ | 6.8kΩ pull-up resistor for Q8 base, correctly connected between Q8 base and +5VCC with appropriate value. | </details> <details> <summary>X1 - 405C35B12M00000 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/405C35B12M00000) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | C1 | NetC42_2 | ✅ | Crystal pin C1 correctly connects to microcontroller XIN pin through load capacitor C42. | | 2 | GND | GND | ✅ | Ground pins correctly connected to circuit ground for EMI suppression. | | 4 | GND | GND | ✅ | Ground pins correctly connected to circuit ground for EMI suppression. | | 3 | C2 | NetC41_2 | ✅ | Crystal pin C2 correctly connects to microcontroller XOUT pin through load capacitor C41. | </details> <details> <summary>C41 - 3pF 0603 50V NP0 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/06031A3R0BAT2A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="16.72,30.65,24.22,38.15" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic)</li><li>Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic)</li><li>This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The connection topology is correct for a crystal oscillator load capacitor (reasoning)</li><li>The capacitor value is 3pF ±0.1pF (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet <a href="https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1">405C35B12M00000</a>, page 1)</li><li>For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning)</li><li>With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning)</li><li>This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning)</li><li>To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning)</li><li>The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)</li><li>Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)</li></ul></details> | | 2 | 2 | NetC41_2 | ❌ | <details><summary>Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="16.72,30.18,24.22,37.68" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic)</li><li>Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic)</li><li>This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The connection topology is correct for a crystal oscillator load capacitor (reasoning)</li><li>The capacitor value is 3pF ±0.1pF (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet <a href="https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1">405C35B12M00000</a>, page 1)</li><li>For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning)</li><li>With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning)</li><li>This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning)</li><li>To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning)</li><li>The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)</li><li>Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)</li></ul></details> | </details> <details> <summary>C42 - 3pF 0603 50V NP0 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/06031A3R0BAT2A) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ❌ | <details><summary>Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="13.09,30.65,20.59,38.15" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 (from schematic)</li><li>Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) (from schematic)</li><li>This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The connection topology is correct for a crystal oscillator load capacitor (reasoning)</li><li>The capacitor value is 3pF ±0.1pF (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required (reasoning)</li><li>The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side (from datasheet <a href="https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1">405C35B12M00000</a>, page 1)</li><li>The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)</li><li>Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)</li></ul></details> | | 2 | 2 | NetC42_2 | ❌ | <details><summary>Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary>!thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="13.09,30.18,20.59,37.68" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 (from schematic)</li><li>Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) (from schematic)</li><li>This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>The connection topology is correct for a crystal oscillator load capacitor (reasoning)</li><li>The capacitor value is 3pF ±0.1pF (from datasheet <a href="https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1">06031A3R0BAT2A</a>, page 1)</li><li>C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required (reasoning)</li><li>The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side (from datasheet <a href="https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1">405C35B12M00000</a>, page 1)</li><li>The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)</li><li>Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)</li></ul></details> | </details> <details> <summary>FB29 - FERRITE 120R 3A 0603 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/404/CIS10P.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CIS10P121AC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VUSB | ✅ | Connected to VUSB, the filtered USB power rail on the isolated side of the USB interface. This is the output side of the ferrite bead providing filtered power to the USB isolator and related circuitry. | | 2 | 2 | NetC43_2 | ✅ | Connected to NetC43_2, which includes the raw VBUS from USB connector J8 pin 1. This is the input side of the ferrite bead receiving unfiltered USB power from the connector. | </details> <details> <summary>JP1 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Solder jumper between +5VCC (pin 1) and VUSB (pin 2) allowing optional powering of the system from USB. Pin 1 connects to the main system 5V rail, while pin 2 connects to the filtered USB power after ferrite bead FB29. | | 2 | 2 | VUSB | ✅ | Solder jumper between +5VCC (pin 1) and VUSB (pin 2) allowing optional powering of the system from USB. Pin 1 connects to the main system 5V rail, while pin 2 connects to the filtered USB power after ferrite bead FB29. | </details> <details> <summary>JP2 - SJ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Solder jumper between GND (pin 1) and USB_GND (pin 2) as part of a configurable USB isolation scheme. Pin 1 connects to the main system ground, while pin 2 connects to the isolated ground domain on the USB connector side. | | 2 | 2 | USB_GND | ✅ | Solder jumper between GND (pin 1) and USB_GND (pin 2) as part of a configurable USB isolation scheme. Pin 1 connects to the main system ground, while pin 2 connects to the isolated ground domain on the USB connector side. | </details> <details> <summary>U11A - ATML-ATSAM3X-LQFP-144 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 29 | PB29/TDI | TDO/SWO | ❌ | <details><summary>JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="46.54,28.11,54.04,35.61" aspect-ratio="1.55" } <ul><li>Pin 29 is PB29/TDI (Test Data In) (from schematic)</li><li>Pin 29 is connected to net TDO/SWO (from schematic)</li><li>Pin 30 is PB30/TDO/TRACESWO (Test Data Out) (from schematic)</li><li>Pin 30 is connected to net TDI (from schematic)</li><li>PB29 should function as TDI (Test Data In) per datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) (from schematic)</li><li>JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) (from schematic)</li><li>The TDI and TDO pins are swapped, preventing proper JTAG debugging (reasoning)</li><li>Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO (reasoning)</li></ul></details> | | 30 | PB30/TDO/TRACESWO | TDI | ❌ | <details><summary>JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="46.54,29.01,54.04,36.51" aspect-ratio="1.55" } <ul><li>Pin 29 is PB29/TDI (Test Data In) (from schematic)</li><li>Pin 29 is connected to net TDO/SWO (from schematic)</li><li>Pin 30 is PB30/TDO/TRACESWO (Test Data Out) (from schematic)</li><li>Pin 30 is connected to net TDI (from schematic)</li><li>PB29 should function as TDI (Test Data In) per datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet (from datasheet <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8">ATSAM3X8EA-AU</a>, page 8)</li><li>JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) (from schematic)</li><li>JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) (from schematic)</li><li>The TDI and TDO pins are swapped, preventing proper JTAG debugging (reasoning)</li><li>Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO (reasoning)</li></ul></details> | | 1 | PB26/CTS0/TCLK0/WKUP15 | STEP6 | ✅ | PB26 configured as GPIO output for stepper motor step control (STEP6). | | 2 | PA9/UTXD/PWMH3 | PA9_UTXD | ✅ | PA9 configured as UTXD for UART transmit. | | 3 | PA10/RXD0/DATRG/WKUP5 | DIAG7 | ✅ | PA10 configured as GPIO input for diagnostic signal (DIAG7). | | 4 | PA11/TXD0/ADTRG/WKUP6 | DIAG8 | ✅ | PA11 configured as GPIO input for diagnostic signal (DIAG8). | | 5 | PA12/RXD1/PWML1/WKUP7 | PA12_RXD1 | ✅ | PA12 configured as RXD1 for USART1 receive. | | 6 | PA13/TXD1/PWMH2 | PA13_TXD1 | ✅ | PA13 configured as TXD1 for USART1 transmit. | | 7 | PA14/RTS1/TK | PA14_RTS1 | ✅ | PA14 configured as RTS1 for USART1 flow control. | | 8 | PA15/CTS1/TF/WKUP8 | PA15_CTS1 | ✅ | PA15 configured as CTS1 for USART1 flow control. | | 9 | PA17/TWD0/SPCK0 | PA17_SDA | ✅ | PA17 configured as TWD0 (I2C SDA) with proper pull-up resistor. | | 13 | PD0/A10/MCDA4 | M_nCS7 | ✅ | PD0 configured as GPIO output for chip select (M_nCS7). | | 14 | PD1/A11/MCDA5 | DIR8 | ✅ | PD1 configured as GPIO output for stepper motor direction control (DIR8). | | 15 | PD2/A12/MCDA6 | M_nCS8 | ✅ | PD2 configured as GPIO output for chip select (M_nCS8). | | 16 | PD3/A13/MCDA7 | STEP8 | ✅ | PD3 configured as GPIO output for stepper motor step control (STEP8). | | 17 | PD4/A14/TXD3 | MIN_ES1 | ✅ | PD4 configured as GPIO input for minimum endstop (MIN_ES1). | | 18 | PD5/A15/RXD3 | MAX_ES2 | ✅ | PD5 configured as GPIO input for maximum endstop (MAX_ES2). | | 19 | PD6/A16/BA0/PWMFI2 | MIN_ES2 | ✅ | PD6 configured as GPIO input for minimum endstop (MIN_ES2). | | 20 | PD7/A17/BA1/TIOA8 | TACH_3 | ✅ | PD7 configured as GPIO input for tachometer (TACH_3). | | 21 | PD8/A21/NANDALE/TIOB8 | TACH_2 | ✅ | PD8 configured as GPIO input for tachometer (TACH_2). | | 22 | PD9/A22/NANDCLE/TCLK8 | MAX_ES3 | ✅ | PD9 configured as GPIO input for maximum endstop (MAX_ES3). | | 23 | PA0/CANTX0/PWML3 | PA0_CANTX0 | ✅ | PA0 configured as CANTX0 for CAN bus transmit. | | 24 | PA1/CANRX0/PCK0/WKUP0 | PA1_CANRX0 | ✅ | PA1 configured as CANRX0 for CAN bus receive. | | 25 | PA5/TIOA2/PWMFI0/WKUP2 | PA5_PWM | ✅ | PA5 configured as GPIO output for PWM control. | | 26 | PA7/TCLK2/NCS1/WKUP3 | MIN_ES3 | ✅ | PA7 configured as GPIO input for minimum endstop (MIN_ES3). | | 27 | PA8/URXD/PWMH0/WKUP4 | PA8_URXD | ✅ | PA8 configured as URXD for UART receive. | | 28 | PB28/TCK/SWCLK | TCK/SWDCLK | ✅ | PB28 configured as TCK/SWCLK for JTAG/SWD debugging. | | 31 | PB31/TMS/SWDIO | TMS/SWDIO | ✅ | PB31 configured as TMS/SWDIO for JTAG/SWD debugging. | | 32 | PD10/NWR1/NBS1 | MAX_ES1 | ✅ | PD10 configured as GPIO input for maximum endstop (MAX_ES1). | | 55 | PC1 | LED_Y | ✅ | PC1 configured as GPIO output for yellow LED control. | | 59 | PC2/D0/PWML0 | PC2_PWML0 | ✅ | PC2 configured as PWML0 for PWM output. | | 60 | PC3/D1/PWMH0 | LED_R | ✅ | PC3 configured as GPIO output for red LED control. | | 63 | PC5/D3/PWMH1 | DIAG1 | ✅ | PC5 configured as GPIO input for diagnostic signal (DIAG1). | | 64 | PC6/D4/PWML2 | DIR1 | ✅ | PC6 configured as GPIO output for stepper motor direction control (DIR1). | | 65 | PC7/D5/PWMH2 | STEP1 | ✅ | PC7 configured as GPIO output for stepper motor step control (STEP1). | | 66 | PC8/D6/PWML3 | PC8_PWML3 | ✅ | PC8 configured as PWML3 for PWM output. | | 67 | PC9/D7/PWMH3 | DRV_EN | ✅ | PC9 configured as GPIO output for driver enable signal (DRV_EN). | | 68 | PB27/NCS3/TIOB0 | PB27_TIOB0 | ✅ | PB27 configured as TIOB0 for timer I/O. | | 70 | PA18/TWCK0/A20/WKUP9 | PA18_SCL | ✅ | PA18 configured as TWCK0 (I2C SCL) with proper pull-up resistor. | | 71 | PA19/MCCK/PWMH1 | MCCK | ✅ | PA19 configured as MCCK for SD card clock. | | 72 | PA20/MCCDA/PWML2 | MCCDA | ✅ | PA20 configured as MCCDA for SD card command/data. | | 76 | PB15/CANRX1/PWMH3/DAC0/WKUP12 | Fan3 | ✅ | PB15 configured as DAC0 or PWM for fan control (Fan3). | | 77 | PB16/TCLK5/PWML0/DAC1 | Fan4 | ✅ | PB16 configured as DAC1 or PWM for fan control (Fan4). | | 78 | PA16/SPCK1/TD/AD7 | PA16 | ✅ | PA16 configured as general purpose I/O. | | 79 | PA24/MCDA3/PCK1/AD6 | MCDA3 | ✅ | PA24 configured as MCDA3 for SD card data line 3. | | 80 | PA23/MCDA2/TCLK4/AD5 | MCDA2 | ✅ | PA23 configured as MCDA2 for SD card data line 2. | | 81 | PA22/MCDA1/TCLK3/AD4 | MCDA1 | ✅ | PA22 configured as MCDA1 for SD card data line 1. | | 82 | PA6/TIOB2/NCS0/AD3 | TC_nCS3 | ✅ | PA6 configured as GPIO output for thermocouple chip select (TC_nCS3). | | 83 | PA4/TCLK1/NWAIT/AD2 | M_nCS1 | ✅ | PA4 configured as GPIO output for motor driver chip select (M_nCS1). | | 84 | PA3/TIOB1/PWMFI1/AD1/WKUP1 | PA3_AD2 | ✅ | PA3 configured as analog input AD1, but net is named PA3_AD2 which may be a naming inconsistency. | | 85 | PA2/TIOA1/NANDRDY/AD0 | TC_nCS4 | ✅ | PA2 configured as GPIO output for thermocouple chip select (TC_nCS4). | | 86 | PB12/TWD1/PWMH0/AD8 | PB12_AD8 | ✅ | PB12 configured as analog input AD8. | | 87 | PB13/TWCK1/PWMH1/AD9 | PB13_AD9 | ✅ | PB13 configured as analog input AD9. | | 88 | PB17/RF/PWML1/AD10 | TC_nCS5 | ✅ | PB17 configured as GPIO output for thermocouple chip select (TC_nCS5). | | 89 | PB18/RD/PWML2/AD11 | THERM_AN2 | ✅ | PB18 configured as analog input AD11 for thermocouple (THERM_AN2). | | 90 | PB19/RK/PWML3/AD12 | THERM_AN1 | ✅ | PB19 configured as analog input AD12 for thermocouple (THERM_AN1). | | 91 | PB20/TXD2/SPI0_NPCS1/AD13 | THERM_AN3 | ✅ | PB20 configured as analog input AD13 for thermocouple (THERM_AN3). | | 92 | PB21/RXD2/SPI0_NPCS2/AD14/WKUP13 | SPIFLASH_CS | ✅ | PB21 configured as GPIO output for SPI flash chip select (SPIFLASH_CS). | | 93 | PC11/D9/ERX2 | DIAG2 | ✅ | PC11 configured as GPIO input for diagnostic signal (DIAG2). | | 94 | PC12/D10/ERX3 | DIR2 | ✅ | PC12 configured as GPIO output for stepper motor direction control (DIR2). | | 95 | PC13/D11/ECOL | STEP2 | ✅ | PC13 configured as GPIO output for stepper motor step control (STEP2). | | 96 | PC14/D12/ERXCK | M_nCS2 | ✅ | PC14 configured as GPIO output for motor driver chip select (M_nCS2). | | 97 | PC15/D13/ETX2 | DIAG3 | ✅ | PC15 configured as GPIO input for diagnostic signal (DIAG3). | | 98 | PC16/D14/ETX3 | DIR3 | ✅ | PC16 configured as GPIO output for stepper motor direction control (DIR3). | | 99 | PC17/D15/ETXER | STEP3 | ✅ | PC17 configured as GPIO output for stepper motor step control (STEP3). | | 100 | PC18/NWR0/NWE/PWMH6 | M_nCS3 | ✅ | PC18 configured as GPIO output for motor driver chip select (M_nCS3). | | 101 | PC19/NANDOE/PWMH5 | DIAG4 | ✅ | PC19 configured as GPIO input for diagnostic signal (DIAG4). | | 102 | PC29/A8/TIOB7 | TACH_4 | ✅ | PC29 configured as GPIO input for tachometer (TACH_4). | | 103 | PC30/A9/TCLK7 | HOLD# | ✅ | PC30 configured as GPIO output for SPI flash hold signal (HOLD#). | | 107 | PA21/MCDA0/PWML0 | MCDA0 | ✅ | PA21 configured as MCDA0 for SD card data line 0. | | 108 | PA25/SPI0_MISO/A18 | NetR83_2 | ✅ | PA25 configured as SPI0_MISO with series termination resistor. | | 109 | PA26/SPI0_MOSI/A19 | NetR77_2 | ✅ | PA26 configured as SPI0_MOSI with series termination resistor. | | 110 | PA27/SPI0_SPCK/A20/WKUP10 | NetR82_2 | ✅ | PA27 configured as SPI0_SPCK with series termination resistor. | | 111 | PA28/SPI0_NPCS0/PCK2/WKUP11 | PA28_CS0 | ✅ | PA28 configured as SPI0_NPCS0 for SPI chip select 0. | | 112 | PA29/SPI0_NPCS1/NRD | PA29_CS | ✅ | PA29 configured as SPI0_NPCS1 for SPI chip select 1. | | 113 | PB0/ETXCK/EREFCK | PB0_ETXCK | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 114 | PB1/ETXEN | PB1_ETXEN | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 115 | PB2/ETX0 | PB2_ETX0 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 118 | PB3/ETX1 | STEP5 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 119 | PB4/ECRSDV/ERXDV | M_nCS6 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 120 | PB5/ERX0 | M_nCS5 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 121 | PB6/ERX1 | DIR7 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 122 | PB7/ERXER | MAX_ES4 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 123 | PB8/EMDC | STEP7 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 127 | PB9/EMDIO | TC_nCS2 | ✅ | Ethernet pins repurposed for non-Ethernet functions. This is acceptable if Ethernet functionality is not required in the design. | | 116 | PC4/D2/PWML1 | DIR4 | ✅ | PC4 configured as GPIO output for stepper motor direction control (DIR4). | | 117 | PC10/D8/ECRS | STEP4 | ✅ | PC10 configured as GPIO output for stepper motor step control (STEP4). | | 128 | PB10/UOTGVBOF/A18 | M_nCS4 | ✅ | PB10 configured as GPIO output for motor driver chip select (M_nCS4). | | 129 | PB11/UOTGID/A19 | SDCD | ✅ | PB11 configured as GPIO input for SD card detect (SDCD). | | 130 | PC0/ERASE | ERASE | ✅ | PC0 configured as ERASE pin for flash programming. | | 131 | PC20/NANDWE/PWMH4 | DIAG5 | ✅ | PC20 configured as GPIO input for diagnostic signal (DIAG5). | | 132 | PC21/A0/NBS0/PWML4 | HEAT1 | ✅ | PC21 configured as PWM output for heater control (HEAT1). | | 133 | PC22/A1/PWML5 | HEAT2 | ✅ | PC22 configured as PWM output for heater control (HEAT2). | | 134 | PC23/A2/PWML6 | HEATBED | ✅ | PC23 configured as PWM output for heated bed control (HEATBED). | | 135 | PC24/A3/PWML7 | HEAT3 | ✅ | PC24 configured as PWM output for heater control (HEAT3). | | 136 | PC25/A4/TIOA6 | FAN2 | ✅ | PC25 configured as timer output for fan control (FAN2). | | 137 | PC26/A5/TIOB6 | FAN1 | ✅ | PC26 configured as timer output for fan control (FAN1). | | 138 | PC27/A6/TCLK6 | TC_nCS1 | ✅ | PC27 configured as GPIO output for thermocouple chip select (TC_nCS1). | | 139 | PC28/A7/TIOA7 | TACH_1 | ✅ | PC28 configured as GPIO input for tachometer (TACH_1). | | 140 | PB14/CANTX1/PWMH2 | MIN_ES4 | ✅ | PB14 configured as GPIO input for minimum endstop (MIN_ES4). | | 141 | PB22/RTS2/PCK0 | DIR5 | ✅ | PB22 configured as GPIO output for stepper motor direction control (DIR5). | | 142 | PB23/CTS2/SPI0_NPCS3/WKUP14 | DIAG6 | ✅ | PB23 configured as GPIO input for diagnostic signal (DIAG6). | | 143 | PB24/SCK2/NCS2 | DIR6 | ✅ | PB24 configured as GPIO output for stepper motor direction control (DIR6). | | 144 | PB25/RTS0/TIOA0 | PB25_TIOA0 | ✅ | PB25 configured as TIOA0 for timer I/O. | </details> <details> <summary>U11C - ATML-ATSAM3X-LQFP-144 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 10 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT (voltage regulator output). | | 45 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT (voltage regulator output). | | 61 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT (voltage regulator output). | | 104 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT (voltage regulator output). | | 124 | VDDCORE | VDDOUT | ✅ | VDDCORE pins correctly connected to VDDOUT (voltage regulator output). | | 11 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO (I/O power supply). | | 62 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO (I/O power supply). | | 105 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO (I/O power supply). | | 125 | VDDIO | 3.3VIO | ✅ | VDDIO pins correctly connected to 3.3VIO (I/O power supply). | | 12 | GND | GND | ✅ | GND pins correctly connected to ground. | | 58 | GND | GND | ✅ | GND pins correctly connected to ground. | | 106 | GND | GND | ✅ | GND pins correctly connected to ground. | | 126 | GND | GND | ✅ | GND pins correctly connected to ground. | | 33 | GNDPLL | GND | ✅ | GNDPLL pin correctly connected to ground. | | 34 | VDDPLL | VDDPLL | ✅ | VDDPLL pin correctly connected with filtering through ferrite bead from VDDOUT. | | 41 | VDDUTMI | VDDUTMI | ✅ | VDDUTMI pin correctly connected with filtering through ferrite bead from 3.3VCC. | | 44 | GNDUTMI | GND | ✅ | GNDUTMI pin correctly connected to ground. | | 52 | VDDBU | 3.3VCC | ✅ | VDDBU pin correctly connected to 3.3VCC for backup power. | | 54 | GNDBU | GND | ✅ | GNDBU pin correctly connected to ground. | | 56 | VDDOUT | VDDOUT | ✅ | VDDOUT pin correctly connected with required decoupling capacitors. | | 57 | VDDIN | 3.3VCC | ✅ | VDDIN pin correctly connected to 3.3VCC with required decoupling capacitor. | | 73 | VDDANA | VDDANA | ✅ | VDDANA pin correctly connected with filtering through ferrite bead from 3.3VCC. | | 74 | GNDANA | GND | ✅ | GNDANA pin correctly connected to ground. | </details> <details> <summary>J4 - ARM Cortex JTAG-DEBUG Header ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 6 | 6 | TDO/SWO | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="39.19,71.26,46.69,78.76" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net (from schematic)</li><li>Pin 8 is connected to the TDI net (from schematic)</li><li>The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic)</li><li>The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic)</li><li>ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning)</li><li>In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning)</li><li>The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning)</li><li>The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning)</li><li>The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning)</li><li>To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 8 | 8 | TDI | ❌ | <details><summary>TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.</summary>!thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="39.19,70.36,46.69,77.86" aspect-ratio="1.55" } <ul><li>Pin 6 is connected to the TDO/SWO net (from schematic)</li><li>Pin 8 is connected to the TDI net (from schematic)</li><li>The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic)</li><li>The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic)</li><li>ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning)</li><li>In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning)</li><li>The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning)</li><li>The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning)</li><li>The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning)</li><li>To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)</li></ul></details> | | 1 | 1 | 3.3VCC | ✅ | VTref (target reference voltage) pin correctly connected to 3.3VCC power rail to provide voltage reference to the debugger. | | 2 | 2 | TMS/SWDIO | ✅ | TMS/SWDIO pin correctly connected to microcontroller PB31 with appropriate 100K pull-up resistor. | | 3 | 3 | GND | ✅ | Ground pin correctly connected to GND net. | | 4 | 4 | TCK/SWDCLK | ✅ | TCK/SWDCLK pin correctly connected to microcontroller PB28 with appropriate 100K pull-up resistor. | | 5 | 5 | GND | ✅ | Ground pin correctly connected to GND net. | | 7 | 7 | unconnected-(NetJ4_7) | ✅ | Pin 7 is unconnected, which is acceptable as this pin is typically a key position or optional nTRST signal. | | 9 | 9 | GND | ✅ | Ground pin correctly connected to GND net. | | 10 | 10 | RESET | ✅ | nRESET pin connected to RESET net with reset button and capacitor. The RESET net appears separate from the NRST net used elsewhere in the design, which may indicate these nets are connected on another schematic page or through external circuitry. | </details> <details> <summary>U12 - AT25SF161-SSHD-T ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25sf161b-datasheet?language=en) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AT25SF161-SSHD-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPIFLASH_CS | ✅ | CS# (Chip Select) is connected to SPIFLASH_CS with pull-up through diode OR-ing network. While the datasheet recommends a direct 10K pull-up, the indirect pull-up through D77 and R100 should be functionally adequate for the shared SPI bus design. | | 2 | SO | MISO_M1BUS | ✅ | SO (Serial Output) is correctly connected to MISO_M1BUS, which is part of a shared SPI bus with tri-state buffer U16 to prevent bus conflicts. | | 3 | WP# | WP# | ✅ | WP# (Write Protect) is correctly pulled high through R85 (10K to 3.3VCC), disabling write protection as intended. | | 4 | GND | GND | ✅ | GND is correctly connected to the system ground plane. | | 5 | SI/IO0 | MOSI_M1BUS | ✅ | SI (Serial Input) is correctly connected to MOSI_M1BUS with appropriate 47R series resistor for signal integrity. | | 6 | SCK | SCLK_M1BUS | ✅ | SCK (Serial Clock) is correctly connected to SCLK_M1BUS with appropriate 47R series resistor, clock buffering, and decoupling. | | 7 | HOLD# | HOLD# | ✅ | HOLD# is connected to microcontroller GPIO PC30, allowing software control of the HOLD function or use as IO3 in quad-SPI mode. This is a valid design choice. | | 8 | VCC | 3.3VCC | ✅ | VCC is correctly connected to 3.3VCC with appropriate 100nF decoupling capacitor C164. | </details> <details> <summary>D77 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode is correctly connected to CS_M1BUS, which is part of the shared SPI bus chip select OR-ing logic with 10K pull-up R100. | | K | K | SPIFLASH_CS | ✅ | Cathode is correctly connected to SPIFLASH_CS, allowing the SPI flash to be selected through either CS_M1BUS or directly by the microcontroller, and enabling proper MISO buffer control. | </details> <details> <summary>J18 - 0475710001 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-47309-001.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0475710001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | MCDA2 | ✅ | DAT2 signal line correctly connected to MCDA2 on the microcontroller with appropriate ESD protection and pull-up resistor. | | 2 | CD/DAT3 | MCDA3 | ✅ | CD/DAT3 signal line correctly connected to MCDA3 on the microcontroller with appropriate ESD protection and pull-up resistor. | | 3 | CMD | MCCDA | ✅ | CMD signal line correctly connected to MCCDA on the microcontroller with appropriate ESD protection and pull-up resistor. | | 4 | VDD | 3.3VCC | ✅ | VDD power pin correctly connected to 3.3VCC with adequate decoupling capacitor. | | 5 | CLK | MCCK | ✅ | CLK signal line correctly connected to MCCK on the microcontroller with appropriate ESD protection. | | 6 | VSS | GND | ✅ | VSS ground pin correctly connected to GND. | | 7 | DAT1 | MCDA0 | ✅ | DAT0 and DAT1 data lines are electrically connected correctly by pin number, but the schematic symbol has misleading pin labels showing them swapped. | | 8 | DAT0 | MCDA1 | ✅ | DAT0 and DAT1 data lines are electrically connected correctly by pin number, but the schematic symbol has misleading pin labels showing them swapped. | | 9 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 10 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 11 | SH | GND | ✅ | Shield pins correctly connected to GND for proper EMI shielding and mechanical grounding. | | 12 | CD | SDCD | ✅ | Card detect pin correctly connected to SDCD with pull-up resistor and ESD protection for active-low card presence detection. | | 13 | CD/POL | GND | ✅ | Card detect polarity pin correctly connected to GND to set active-low polarity. | </details> <details> <summary>D42 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the SDCD signal line. | | C | C | SDCD | ✅ | Cathode correctly connected to SDCD signal line for ESD protection on the card detect signal. | </details> <details> <summary>D64 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCDA1 signal line. | | C | C | MCDA1 | ✅ | Cathode correctly connected to MCDA1 signal line for ESD protection on SD card data line 1. | </details> <details> <summary>D65 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCDA0 signal line. | | C | C | MCDA0 | ✅ | Cathode correctly connected to MCDA0 signal line for ESD protection on SD card data line 0. | </details> <details> <summary>D66 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCCDA signal line. | | C | C | MCCDA | ✅ | Cathode correctly connected to MCCDA signal line for ESD protection on SD card command line. | </details> <details> <summary>D67 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCCK signal line. | | C | C | MCCK | ✅ | Cathode correctly connected to MCCK signal line for ESD protection on SD card clock line. | </details> <details> <summary>D68 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCDA3 signal line. | | C | C | MCDA3 | ✅ | Cathode correctly connected to MCDA3 signal line for ESD protection on SD card data line 3. | </details> <details> <summary>D69 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to GND for unidirectional ESD protection on the MCDA2 signal line. | | C | C | MCDA2 | ✅ | Cathode correctly connected to MCDA2 signal line for ESD protection on SD card data line 2. | </details> <details> <summary>J12 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external devices connected to this header. | | 2 | 2 | GND | ✅ | Ground pin connected to GND net. Provides ground reference for external devices. | | 3 | 3 | NetJ12_3 | ✅ | Signal pin connected to PC2_PWML0 through 100R series resistor R137. Provides buffered PWM output signal. | | 4 | 4 | NetJ12_4 | ✅ | Signal pin connected to PA1_CANRX0 through 100R series resistor R136. Provides buffered CAN receive signal. | | 5 | 5 | NetJ12_5 | ✅ | Signal pin connected to PA16 through 100R series resistor R135. Provides buffered general purpose I/O signal. | | 6 | 6 | NetJ12_6 | ✅ | Signal pin connected to PA0_CANTX0 through 100R series resistor R134. Provides buffered CAN transmit signal. | | 7 | 7 | NetJ12_7 | ✅ | Signal pin connected to PA12_RXD1 through 100R series resistor R133. Provides buffered UART receive signal. | | 8 | 8 | NetJ12_8 | ✅ | Signal pin connected to PA15_CTS1 through 100R series resistor R120. Provides buffered UART clear-to-send signal. | | 9 | 9 | NetJ12_9 | ✅ | Signal pin connected to PA13_TXD1 through 100R series resistor R114. Provides buffered UART transmit signal. | | 10 | 10 | NetJ12_10 | ✅ | Signal pin connected to PA14_RTS1 through 100R series resistor R109. Provides buffered UART request-to-send signal. | </details> <details> <summary>J13 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VCC | ✅ | Power supply pin connected to +5VCC rail. Provides 5V power to external devices. | | 2 | 2 | GND | ✅ | Ground pin connected to GND net. Provides ground reference. | | 3 | 3 | NetJ13_3 | ✅ | Signal pin connected to NRST through 100R series resistor R145. Provides buffered reset signal output. | | 4 | 4 | NetJ13_4 | ✅ | Signal pin connected to PB25_TIOA0 through 100R series resistor R144. Provides buffered timer I/O signal. | | 5 | 5 | NetJ13_5 | ✅ | Signal pin connected to PA26_MOSI through 100R series resistor R143. Provides buffered SPI MOSI signal. | | 6 | 6 | NetJ13_6 | ✅ | Signal pin connected to PA3_AD2 through 100R series resistor R142. Provides buffered ADC input signal. | | 7 | 7 | NetJ13_7 | ✅ | Signal pin connected to PA29_CS through 100R series resistor R141. Provides buffered SPI chip select signal. | | 8 | 8 | NetJ13_8 | ✅ | Signal pin connected to PB27_TIOB0 through 100R series resistor R140. Provides buffered timer I/O signal. | | 9 | 9 | NetJ13_9 | ✅ | Signal pin connected to PA27_SCLK through 100R series resistor R139. Provides buffered SPI clock signal. | | 10 | 10 | NetJ13_10 | ✅ | Signal pin connected to PA25_MISO through 100R series resistor R138. Provides buffered SPI MISO signal. | </details> <details> <summary>J28 - Header 10PIN 2ROW T-HOLE VERT SHROUDED ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/6025/302-S.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/302-S101) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins connected to GND net. Provide ground reference for serial interface. | | 10 | 10 | GND | ✅ | Ground pins connected to GND net. Provide ground reference for serial interface. | | 2 | 2 | PA9_UTXD | ✅ | UART transmit signal connected directly to PA9_UTXD. Protected by ESD diode D72. | | 3 | 3 | +5VCC | ✅ | 5V power pins connected to +5VCC rail. Provide 5V power for external device. | | 8 | 8 | +5VCC | ✅ | 5V power pins connected to +5VCC rail. Provide 5V power for external device. | | 4 | 4 | PA8_URXD | ✅ | UART receive signal connected directly to PA8_URXD. Protected by ESD diode D73. | | 5 | 5 | 3.3VCC | ✅ | 3.3V power supply pin connected to 3.3VCC rail. Provides 3.3V power reference. | | 6 | 6 | NRST | ✅ | Reset signal connected directly to NRST. Protected by ESD diode D71. | | 7 | 7 | ERASE | ✅ | Erase signal connected directly to ERASE. Used for chip erase function. | | 9 | 9 | PC8_PWML3 | ✅ | PWM signal connected directly to PC8_PWML3. This signal lacks ESD protection, which is inconsistent with other signal pins on this connector, though it may be acceptable if used only as an output. | </details> <details> <summary>J20 - Header 12X2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PA28_CS0 | ✅ | SPI chip select signal connected directly to PA28_CS0 from microcontroller. | | 2 | 2 | PA27_SCLK | ✅ | SPI clock signal connected directly to PA27_SCLK from microcontroller. | | 3 | 3 | PA26_MOSI | ✅ | SPI MOSI signal connected directly to PA26_MOSI from microcontroller. | | 4 | 4 | PA25_MISO | ✅ | SPI MISO signal connected directly to PA25_MISO from microcontroller. | | 5 | 5 | unconnected-(NetJ20_5) | ✅ | Unconnected pins. These pins are not used in the current design. | | 6 | 6 | unconnected-(NetJ20_6) | ✅ | Unconnected pins. These pins are not used in the current design. | | 7 | 7 | unconnected-(NetJ20_7) | ✅ | Unconnected pins. These pins are not used in the current design. | | 9 | 9 | unconnected-(NetJ20_9) | ✅ | Unconnected pins. These pins are not used in the current design. | | 10 | 10 | unconnected-(NetJ20_10) | ✅ | Unconnected pins. These pins are not used in the current design. | | 11 | 11 | unconnected-(NetJ20_11) | ✅ | Unconnected pins. These pins are not used in the current design. | | 12 | 12 | unconnected-(NetJ20_12) | ✅ | Unconnected pins. These pins are not used in the current design. | | 13 | 13 | unconnected-(NetJ20_13) | ✅ | Unconnected pins. These pins are not used in the current design. | | 14 | 14 | unconnected-(NetJ20_14) | ✅ | Unconnected pins. These pins are not used in the current design. | | 17 | 17 | unconnected-(NetJ20_17) | ✅ | Unconnected pins. These pins are not used in the current design. | | 8 | 8 | PB12_AD8 | ✅ | ADC input signal connected directly to PB12_AD8 from microcontroller. | | 15 | 15 | NetJ20_15 | ✅ | Ethernet transmit data signal ETX0 connected through 100R resistor R161 and protected by varistor RV3. | | 16 | 16 | NetJ20_16 | ✅ | Ethernet transmit enable signal ETXEN connected through 100R resistor R160 and protected by varistor RV4. | | 18 | 18 | NRST | ✅ | Reset signal connected directly to NRST. Allows external reset of the microcontroller. | | 19 | 19 | NetJ20_19 | ✅ | ADC input signal AD9 connected through 100R resistor R159 and protected by varistor RV2. | | 20 | 20 | NetJ20_20 | ✅ | Ethernet transmit clock signal ETXCK connected through 100R resistor R153 and protected by varistor RV1. | | 21 | 21 | PA18_SCL | ✅ | I2C clock signal connected directly to PA18_SCL from microcontroller. | | 22 | 22 | PA17_SDA | ✅ | I2C data signal connected directly to PA17_SDA from microcontroller. | | 23 | 23 | GND | ✅ | Ground pin connected to GND net. Provides ground reference. | | 24 | 24 | 3.3VCC | ✅ | 3.3V power supply pin connected to 3.3VCC rail. Provides 3.3V power. | </details> <details> <summary>D71 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND. Correct orientation for unidirectional ESD protection. | | C | C | NRST | ✅ | Cathode connected to NRST signal. Provides ESD protection for the reset line exposed on external connectors. | </details> <details> <summary>D72 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND. Correct orientation for unidirectional ESD protection. | | C | C | PA9_UTXD | ✅ | Cathode connected to PA9_UTXD signal. Provides ESD protection for the UART transmit line exposed on J28. | </details> <details> <summary>D73 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to GND. Correct orientation for unidirectional ESD protection. | | C | C | PA8_URXD | ✅ | Cathode connected to PA8_URXD signal. Provides ESD protection for the UART receive line exposed on J28. | </details> <details> <summary>U14 - 74AVC9112 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://assets.nexperia.com/documents/data-sheet/74AVC9112.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/74AVC9112GTX) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Vcc | 3.3VCC | ✅ | VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C67 (100nF) nearby. | | 2 | A | NetC64_2 | ✅ | Input A correctly connected to PA27_SCLK from microcontroller through series resistor R82 (24R) and capacitor C64 for signal conditioning. | | 3 | nOE | GND | ✅ | Output enable pin nOE correctly tied to GND to permanently enable all four outputs of the clock buffer. | | 4 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 5 | Y1 | NetR3_2 | ✅ | Output Y1 correctly connected to SCLK_TCBUS through series resistor R3 (47R) for termination. | | 6 | Y2 | NetR4_2 | ✅ | Output Y2 correctly connected to PA27_SCLK through series resistor R4 (47R) for termination. | | 7 | Y3 | NetR13_2 | ✅ | Output Y3 correctly connected to SCLK_M1BUS through series resistor R13 (47R) for termination. | | 8 | Y4 | NetR32_2 | ✅ | Output Y4 correctly connected to SCLK_M2BUS through series resistor R32 (47R) for termination. | | 23 | NC | | ✅ | No-connect pin, correctly left unconnected. | </details> <details> <summary>U16 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | CS_TCBUS | ✅ | Output enable for buffer 1, correctly connected to CS_TCBUS to enable MISO_TCBUS when thermocouple bus is active. | | 2 | A1 | MISO_TCBUS | ✅ | Input A1 correctly connected to MISO_TCBUS from thermocouple bus devices. | | 3 | Y1 | NetR94_2 | ✅ | Output Y1 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing. | | 4 | nOE2 | CS_M1BUS | ✅ | Output enable for buffer 2, correctly connected to CS_M1BUS to enable MISO_M1BUS when motor 1 bus is active. | | 5 | A2 | MISO_M1BUS | ✅ | Input A2 correctly connected to MISO_M1BUS from motor 1 bus devices including SPI flash. | | 6 | Y2 | NetR94_2 | ✅ | Output Y2 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing. | | 7 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 8 | Y3 | NetR94_2 | ✅ | Output Y3 correctly connected to PA25_MISO through series resistor R94 (47R), shared with other buffer outputs for MISO multiplexing. | | 9 | A3 | MISO_M2BUS | ✅ | Input A3 correctly connected to MISO_M2BUS from motor 2 bus devices. | | 10 | nOE3 | CS_M2BUS | ✅ | Output enable for buffer 3, correctly connected to CS_M2BUS to enable MISO_M2BUS when motor 2 bus is active. | | 11 | Y4 | unconnected-(NetU16_11) | ✅ | Output Y4 is unconnected but driven low since buffer 4 is enabled with input tied to GND. This is acceptable but buffer 4 could be disabled to save power. | | 12 | A4 | GND | ✅ | Input A4 correctly tied to GND since buffer 4 is unused. | | 13 | nOE4 | GND | ✅ | Output enable for buffer 4 tied to GND, enabling the unused buffer. Could be tied to VCC to disable and save power. | | 14 | Vcc | 3.3VCC | ✅ | VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C78 (100nF) nearby. | | 15 | PAD | GND | ✅ | Thermal pad correctly connected to GND for heat dissipation. | | 23 | NC | | ✅ | No-connect pin, correctly left unconnected. | </details> <details> <summary>U17 - SN74LVC125A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/scas290q/scas290q.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74LVC125ARGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | nOE1 | GND | ✅ | Output enable for buffer 1 correctly tied to GND to permanently enable the buffer for MOSI fan-out. | | 2 | A1 | PA26_MOSI_D | ✅ | Input A1 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution. | | 3 | Y1 | NetR84_2 | ✅ | Output Y1 correctly connected to MOSI_TCBUS through series resistor R84 (47R) for thermocouple bus. | | 4 | nOE2 | GND | ✅ | Output enable for buffer 2 correctly tied to GND to permanently enable the buffer for MOSI fan-out. | | 5 | A2 | PA26_MOSI_D | ✅ | Input A2 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution. | | 6 | Y2 | NetR59_2 | ✅ | Output Y2 correctly connected to MOSI_M1BUS through series resistor R59 (47R) for motor 1 bus. | | 7 | GND | GND | ✅ | Ground pin correctly connected to GND. | | 8 | Y3 | NetR89_2 | ✅ | Output Y3 correctly connected to MOSI_M2BUS through series resistor R89 (47R) for motor 2 bus. | | 9 | A3 | PA26_MOSI_D | ✅ | Input A3 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution. | | 10 | nOE3 | GND | ✅ | Output enable for buffer 3 correctly tied to GND to permanently enable the buffer for MOSI fan-out. | | 11 | Y4 | NetR93_2 | ✅ | Output Y4 correctly connected to PA26_MOSI through series resistor R93 (47R), possibly for local MOSI distribution. | | 12 | A4 | PA26_MOSI_D | ✅ | Input A4 correctly connected to PA26_MOSI_D from microcontroller for MOSI distribution. | | 13 | nOE4 | GND | ✅ | Output enable for buffer 4 correctly tied to GND to permanently enable the buffer for MOSI fan-out. | | 14 | Vcc | 3.3VCC | ✅ | VCC pin correctly connected to 3.3VCC power supply with appropriate decoupling capacitor C91 (100nF) nearby. | | 15 | PAD | GND | ✅ | Thermal pad correctly connected to GND for heat dissipation. | | 23 | NC | | ✅ | No-connect pin, correctly left unconnected. | </details> <details> <summary>D41 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS7 is active. | | K | K | M_nCS7 | ✅ | Cathode correctly connected to M_nCS7 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D40 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS6 is active. | | K | K | M_nCS6 | ✅ | Cathode correctly connected to M_nCS6 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D63 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS8 is active. | | K | K | M_nCS8 | ✅ | Cathode correctly connected to M_nCS8 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D60 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M2BUS | ✅ | Anode correctly connected to CS_M2BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS5 is active. | | K | K | M_nCS5 | ✅ | Cathode correctly connected to M_nCS5 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D70 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS1 is active. | | K | K | M_nCS1 | ✅ | Cathode correctly connected to M_nCS1 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D74 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS2 is active. | | K | K | M_nCS2 | ✅ | Cathode correctly connected to M_nCS2 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D75 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS3 is active. | | K | K | M_nCS3 | ✅ | Cathode correctly connected to M_nCS3 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D76 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_M1BUS | ✅ | Anode correctly connected to CS_M1BUS to form wired-OR gate that automatically enables MISO buffer when M_nCS4 is active. | | K | K | M_nCS4 | ✅ | Cathode correctly connected to M_nCS4 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D62 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS5 is active. | | K | K | TC_nCS5 | ✅ | Cathode correctly connected to TC_nCS5 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D5 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS4 is active. | | K | K | TC_nCS4 | ✅ | Cathode correctly connected to TC_nCS4 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D30 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS2 is active. | | K | K | TC_nCS2 | ✅ | Cathode correctly connected to TC_nCS2 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D31 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS3 is active. | | K | K | TC_nCS3 | ✅ | Cathode correctly connected to TC_nCS3 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>D61 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | CS_TCBUS | ✅ | Anode correctly connected to CS_TCBUS to form wired-OR gate that automatically enables MISO buffer when TC_nCS1 is active. | | K | K | TC_nCS1 | ✅ | Cathode correctly connected to TC_nCS1 microcontroller output to form wired-OR gate for automatic MISO buffer enable. | </details> <details> <summary>S1 - 1571610-2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | RESET | ✅ | Pin 1 (P) connects to the RESET net, which is the active-low reset signal for the JTAG interface. When the button is pressed, it connects to pins 2/3/4 (all at GND), pulling RESET low to assert the reset function. | | 2 | S | GND | ✅ | Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function. | | 3 | 3 | GND | ✅ | Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function. | | 4 | 4 | GND | ✅ | Pins 2, 3, and 4 are all connected to GND, forming the common terminal of the switch. When the button is pressed, these pins connect to pin 1, pulling RESET low to assert the reset function. | </details> <details> <summary>S2 - KMR741NG ULC LFS ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ckswitches.com/media/1908/kmr7.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/KMR741NG%20ULC%20LFS) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | | 3.3VCC | ✅ | Pin 1 connects to 3.3VCC. When the button is pressed, this pin connects to pin 3, pulling the ERASE signal high to 3.3V to assert the erase function. | | 2 | | unconnected-(NetS2_2) | ✅ | Pin 2 is marked as unconnected. This is acceptable for this switch type where only one terminal from each side needs to be connected, as pins 1 and 2 are typically internally connected in the switch. | | 3 | | ERASE | ✅ | Pin 3 connects to the ERASE net. When the button is pressed, this pin connects to pin 1 (3.3VCC), pulling ERASE high to assert the chip erase function on the microcontroller. | | 4 | | unconnected-(NetS2_4) | ✅ | Pin 4 is marked as unconnected. This is acceptable for this switch type where only one terminal from each side needs to be connected, as pins 3 and 4 are typically internally connected in the switch. | </details> <details> <summary>D1 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is connected to GND. This is the reference terminal for the ESD protection diode, providing the return path for ESD current. | | C | C | ERASE | ✅ | Cathode is connected to the ERASE signal. This provides ESD protection for the ERASE net against both negative transients (via forward conduction) and excessive positive transients (via breakdown conduction). | </details> <details> <summary>D24 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD24_A | ✅ | Anode is correctly connected through a 1k current-limiting resistor (R34) to microcontroller GPIO pin PC3 (LED_R signal), allowing the MCU to control the red LED by sourcing current when the GPIO is driven high. | | C | C | GND | ✅ | Cathode is correctly connected to ground, establishing a common-cathode LED configuration. | </details> <details> <summary>D25 - 5988140107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988140107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD25_A | ✅ | Anode is correctly connected through a 1k current-limiting resistor (R36) to microcontroller GPIO pin PC1 (LED_Y signal), allowing the MCU to control the yellow LED by sourcing current when the GPIO is driven high. | | C | C | GND | ✅ | Cathode is correctly connected to ground, establishing a common-cathode LED configuration. | </details> <details> <summary>D44 - ESD9X3.3ST5G ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/esd9x3.3st5g-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ESD9X3.3ST5G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to GND for ESD protection of the 3.3VCC power rail. | | K | K | 3.3VCC | ✅ | Cathode is correctly connected to 3.3VCC power rail for ESD protection. | </details> <details> <summary>D45 - DF2S6.8FS,L3M ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://toshiba.semicon-storage.com/info/docget.jsp?did=22219&prodName=DF2S6.8FS) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DF2S6.8FS,L3M) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to GND for ESD protection of the +5VCC power rail. | | K | K | +5VCC | ✅ | Cathode is correctly connected to +5VCC power rail for ESD protection. | </details> <details> <summary>RV1 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_20 | ✅ | Pin 1 is correctly connected to NetJ20_20, which connects through series resistor R153 (100R) to the PB0_ETXCK Ethernet signal for ESD protection. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages. | </details> <details> <summary>RV2 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_19 | ✅ | Pin 1 is correctly connected to NetJ20_19, which connects through series resistor R159 (100R) to the PB13_AD9 ADC signal for ESD protection. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages. | </details> <details> <summary>RV3 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_15 | ✅ | Pin 1 is correctly connected to NetJ20_15, which connects through series resistor R161 (100R) to the PB2_ETX0 Ethernet signal for ESD protection. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages. | </details> <details> <summary>RV4 - AVRM0603C6R8NT101N ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://product.tdk.com/en/system/files?file=dam/doc/product/protection/voltage/varistor_ctvs/catalog/vpd_varistors_avr_en.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/AVRM0603C6R8NT101N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ20_16 | ✅ | Pin 1 is correctly connected to NetJ20_16, which connects through series resistor R160 (100R) to the PB1_ETXEN Ethernet signal for ESD protection. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to provide a return path for clamping transient voltages. | </details> <details> <summary>J29 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC154_2 | ✅ | Connected to the switched ground output from Q12A drain (NetC154_2), providing PWM-controlled ground connection to the fan motor. | | 2 | S | VFAN | ✅ | Connected to VFAN power supply, providing positive power voltage to the fan motor. | | 3 | S | NetJ29_3 | ✅ | Connected to the tachometer signal from the fan through signal conditioning circuitry including pull-up resistor and voltage clamping protection. | </details> <details> <summary>Q12A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source pin correctly connected to ground for low-side switching configuration. | | 2 | G | NetQ12_2 | ✅ | Gate pin driven through 100Ω resistor from tri-state buffer output, providing proper gate drive with current limiting and EMI reduction. | | 7 | D | NetC154_2 | ✅ | Drain pin connected to fan connector and indicator LED, providing switched ground output for PWM control. | </details> <details> <summary>LED1 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED1_A | ✅ | Anode connected through current-limiting resistor R96 (4.7kΩ) to VFAN, providing approximately 2.1mA LED current for status indication. | | C | C | NetC154_2 | ✅ | Cathode connected to switched output NetC154_2, causing LED to illuminate when MOSFET Q12A is conducting. | </details> <details> <summary>D50 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD50_A | ✅ | Anode connected to the tachometer signal node NetD50_A, forming upper clamp to prevent signal from exceeding 3.3V plus diode forward voltage. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC, providing overvoltage protection for tachometer signal by clamping to 3.3V rail. | </details> <details> <summary>D52 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode connected to ground, forming lower clamp to prevent tachometer signal from going below ground minus diode forward voltage. | | K | K | NetD50_A | ✅ | Cathode connected to tachometer signal node NetD50_A, providing negative voltage protection. | </details> <details> <summary>U2D - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 11 | 4Y | NetR98_1 | ✅ | Output pin 4Y driving the gate of Q12A through 100Ω resistor, providing buffered PWM signal with adequate drive strength. | | 12 | 4A | FAN1 | ✅ | Input pin 4A receiving FAN1 control signal with 10kΩ pull-down resistor ensuring defined logic low state when not actively driven. | | 13 | 4OE | GND | ✅ | Output enable pin 4OE tied to ground, permanently enabling the output to allow the input signal to pass through. | </details> <details> <summary>C155 - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_1 | ✅ | Filter capacitor on TACH_1 signal to ground, reducing high-frequency noise on tachometer input. | | 2 | 2 | GND | ✅ | Filter capacitor on TACH_1 signal to ground, reducing high-frequency noise on tachometer input. | </details> <details> <summary>C154 - C0603TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DNI-C0603TBD) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | Optional output filter capacitor marked DNI, would filter PWM noise between VFAN and switched output if installed. | | 2 | 2 | NetC154_2 | ✅ | Optional output filter capacitor marked DNI, would filter PWM noise between VFAN and switched output if installed. | </details> <details> <summary>TP8 - TestPoint ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | TP | TP | NetC154_2 | ✅ | Test point on the switched fan output NetC154_2 for measurement and debugging. | </details> <details> <summary>R98 - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR98_1 | ✅ | Gate resistor limiting current and reducing ringing on MOSFET gate drive between buffer output and Q12A gate. | | 2 | 2 | NetQ12_2 | ✅ | Gate resistor limiting current and reducing ringing on MOSFET gate drive between buffer output and Q12A gate. | </details> <details> <summary>R174 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_1 | ✅ | Series resistor providing current limiting and isolation for tachometer input signal between TACH_1 and clamping network. | | 2 | 2 | NetD50_A | ✅ | Series resistor providing current limiting and isolation for tachometer input signal between TACH_1 and clamping network. | </details> <details> <summary>R175 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD50_A | ✅ | Series resistor providing current limiting and isolation for tachometer output between clamping network and connector. | | 2 | 2 | NetJ29_3 | ✅ | Series resistor providing current limiting and isolation for tachometer output between clamping network and connector. | </details> <details> <summary>R172 - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ29_3 | ✅ | Pull-up resistor for open-collector tachometer signal, pulling NetJ29_3 to 3.3V logic level. | | 2 | 2 | 3.3VCC | ✅ | Pull-up resistor for open-collector tachometer signal, pulling NetJ29_3 to 3.3V logic level. | </details> <details> <summary>R96 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED1_A | ✅ | Current-limiting resistor for LED1, providing approximately 2.1mA at 12V supply between VFAN and LED anode. | | 2 | 2 | VFAN | ✅ | Current-limiting resistor for LED1, providing approximately 2.1mA at 12V supply between VFAN and LED anode. | </details> <details> <summary>R183 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FAN1 | ✅ | Pull-down resistor ensuring FAN1 control signal defaults to logic low when not driven, keeping fan off by default. | | 2 | 2 | GND | ✅ | Pull-down resistor ensuring FAN1 control signal defaults to logic low when not driven, keeping fan off by default. | </details> <details> <summary>J22 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC153_2 | ✅ | Fan negative terminal, connected to the drain of low-side switch Q12B through NetC153_2. This pin switches the fan ground return. | | 2 | S | VFAN | ✅ | Fan positive supply terminal, connected to VFAN power rail. This provides the positive supply voltage to the fan. | | 3 | S | NetJ22_3 | ✅ | Fan tachometer signal input, connected through signal conditioning network including pull-up resistor R173 and series resistors R177/R176 with clamping diodes. | </details> <details> <summary>Q12B - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 3 | S | GND | ✅ | Source terminal connected to GND. Correctly configured for low-side driver operation. | | 4 | G | NetQ12_4 | ✅ | Gate terminal driven by buffer U2C through 100Ω gate resistor R99. Correctly configured with appropriate gate drive. | | 5 | D | NetC153_2 | ✅ | Drain terminal switching the fan load. Correctly connected to fan connector and status LED. | </details> <details> <summary>U2C - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 8 | 3Y | NetR99_1 | ✅ | Output pin 3Y driving gate resistor R99, buffering the FAN2 control signal to drive the MOSFET gate. | | 9 | 3A | FAN2 | ✅ | Input pin 3A receiving FAN2 control signal, which is pulled down to GND through R182. | | 10 | 3OE | GND | ✅ | Output enable pin 3OE tied to GND, keeping the buffer permanently enabled. | </details> <details> <summary>LED2 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED2_A | ✅ | Anode connected to VFAN through current limiting resistor R12 (4.7kΩ), providing proper current limiting for the indicator LED. | | C | C | NetC153_2 | ✅ | Cathode connected to the switched output NetC153_2, so the LED illuminates when Q12B is turned on. | </details> <details> <summary>D51 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD51_A | ✅ | Anode connected to NetD51_A in the tachometer signal conditioning circuit, forming part of the voltage divider and clamping network. | | K | K | 3.3VCC | ✅ | Cathode connected to 3.3VCC, providing positive voltage clamping for the tachometer signal to prevent overvoltage. | </details> <details> <summary>D53 - BAT54WX ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | unconnected-(NetD53_A) | ❌ | <details><summary>Anode is unconnected (floating), which is incorrect. This pin should be connected to GND to provide negative voltage clamping for the tachometer signal, matching the configuration of D52, D56, and D57 in the other three fan channels.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="63.06,35.82,70.56,43.32" aspect-ratio="1.29" } <ul><li>Pin A is the anode terminal of the Schottky diode (from datasheet <a href="https://www.mccsemi.com/pdf/Products/BAT54WX(SOD-523).pdf#page=1">BAT54WX-TP</a>, page 1)</li><li>Pin A is connected to net unconnected-(NetD53_A), indicating it is floating (from schematic)</li><li>In the parallel channel 1 circuit, D52 has its anode connected to GND and cathode to NetD50_A (from schematic)</li><li>In channel 3, D56 has its anode connected to GND and cathode to NetD54_A (from schematic)</li><li>In channel 4, D57 has its anode connected to GND and cathode to NetD55_A (from schematic)</li><li>D51 and D53 should form a dual-diode clamp circuit for channel 2, with D51 clamping to 3.3VCC and D53 clamping to GND (reasoning)</li><li>The purpose of this diode is to clamp negative-going voltages on the tachometer signal to ground, protecting downstream circuitry (reasoning)</li><li>With the anode floating, D53 cannot perform its clamping function and the circuit lacks protection against negative voltage transients (reasoning)</li><li>The anode of D53 should be connected to GND to match the design pattern of the other three identical tachometer circuits (reasoning)</li></ul></details> | | K | K | NetD51_A | ✅ | Cathode connected to NetD51_A, which is correct for the lower clamping diode in the tachometer signal conditioning circuit. However, the diode cannot function properly without the anode connected to GND. | </details> <details> <summary>C156 - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_2 | ✅ | Connected to TACH_2 signal, providing filtering for the tachometer input. | | 2 | 2 | GND | ✅ | Connected to GND, completing the filter capacitor configuration. | </details> <details> <summary>C153 - C0603TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DNI-C0603TBD) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | Connected to VFAN power rail. This is an optional DNI capacitor for additional filtering. | | 2 | 2 | NetC153_2 | ✅ | Connected to NetC153_2, the switched output node. | </details> <details> <summary>TP1 - TestPoint ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | TP | TP | VFAN | ✅ | Test point connected to VFAN for voltage measurement. | </details> <details> <summary>TP2 - TestPoint ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | TP | TP | NetC153_2 | ✅ | Test point connected to NetC153_2 for measuring the switched output. | </details> <details> <summary>R99 - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR99_1 | ✅ | Connected to U2C output pin 8 (3Y) through NetR99_1. | | 2 | 2 | NetQ12_4 | ✅ | Connected to Q12B gate pin 4 through NetQ12_4, providing gate drive current limiting. | </details> <details> <summary>R176 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_2 | ✅ | Connected to TACH_2 signal, part of the tachometer signal conditioning network. | | 2 | 2 | NetD51_A | ✅ | Connected to NetD51_A, the intermediate node with clamping diodes. | </details> <details> <summary>R177 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD51_A | ✅ | Connected to NetD51_A, the intermediate node with clamping diodes. | | 2 | 2 | NetJ22_3 | ✅ | Connected to NetJ22_3, the tachometer input from the fan connector. | </details> <details> <summary>R173 - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ22_3 | ✅ | Connected to NetJ22_3, providing pull-up for the tachometer signal. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC, providing the pull-up voltage reference. | </details> <details> <summary>R12 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED2_A | ✅ | Connected to LED2 anode through NetLED2_A, providing current limiting for the indicator LED. | | 2 | 2 | VFAN | ✅ | Connected to VFAN, providing the supply voltage for the LED circuit. | </details> <details> <summary>R182 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FAN2 | ✅ | Connected to FAN2 control signal, providing pull-down to ensure defined logic state. | | 2 | 2 | GND | ✅ | Connected to GND, providing the pull-down reference. | </details> <details> <summary>J31 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | NetC211_2 | ✅ | Connected to the switched fan ground through the low-side MOSFET Q13A drain, providing the ground return path for the fan when Q13A is enabled. | | 2 | S | VFAN | ✅ | Connected to VFAN power supply, providing the positive voltage to power the fan. | | 3 | S | NetJ31_3 | ✅ | Connected to the fan tachometer signal conditioning circuit through NetJ31_3, receiving the tachometer output from the fan. | </details> <details> <summary>Q13A - NCV8402AD ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | GND | ✅ | Source pin correctly connected to ground for low-side switch operation. | | 2 | G | NetQ13_2 | ✅ | Gate pin correctly driven through 100Ω resistor R180 from buffer U2B output for controlled MOSFET switching. | | 7 | D | NetC211_2 | ✅ | Drain pin correctly connected to fan load and LED indicator through connector J31. | </details> <details> <summary>U2B - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 4 | 2OE | GND | ✅ | Output enable pin correctly tied to ground to permanently enable the buffer output. | | 5 | 2A | Fan3 | ✅ | Input pin correctly connected to Fan3 control signal with 10kΩ pull-down resistor R171. | | 6 | 2Y | NetR180_1 | ✅ | Output pin correctly drives MOSFET gate through 100Ω series resistor R180. | </details> <details> <summary>LED3 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED3_A | ✅ | Anode correctly connected through 4.7kΩ current limiting resistor R15 to VFAN supply. | | C | C | NetC211_2 | ✅ | Cathode correctly connected to switched output, allowing LED to indicate when fan is active. | </details> <details> <summary>D54 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD54_A | ✅ | Anode correctly connected to midpoint of tachometer voltage divider for signal conditioning. | | K | K | 3.3VCC | ✅ | Cathode correctly connected to 3.3VCC to clamp tachometer signal high. | </details> <details> <summary>D56 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode correctly connected to ground to clamp tachometer signal low. | | K | K | NetD54_A | ✅ | Cathode correctly connected to midpoint of tachometer voltage divider, forming bidirectional clamp with D54. | </details> <details> <summary>C212 - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_3 | ✅ | Connected to TACH_3 signal for filtering tachometer input noise. | | 2 | 2 | GND | ✅ | Connected to ground to complete the filter capacitor. | </details> <details> <summary>C211 - C0603TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DNI-C0603TBD) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | Connected to VFAN supply for optional snubber/filter capacitor across fan load (marked DNI). | | 2 | 2 | NetC211_2 | ✅ | Connected to switched fan ground for optional snubber/filter capacitor (marked DNI). | </details> <details> <summary>TP18 - TestPoint ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | TP | TP | NetC211_2 | ✅ | Test point connected to NetC211_2 for probing the switched fan ground output. | </details> <details> <summary>R180 - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR180_1 | ✅ | Connected to buffer output U2B pin 6 for gate drive. | | 2 | 2 | NetQ13_2 | ✅ | Connected to MOSFET gate Q13A pin 2 for controlled switching. | </details> <details> <summary>R186 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_3 | ✅ | Connected to TACH_3 input signal from tachometer. | | 2 | 2 | NetD54_A | ✅ | Connected to midpoint of voltage divider and bidirectional clamp circuit. | </details> <details> <summary>R187 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD54_A | ✅ | Connected to midpoint of voltage divider and bidirectional clamp circuit. | | 2 | 2 | NetJ31_3 | ✅ | Connected to fan connector tachometer pin through NetJ31_3. | </details> <details> <summary>R184 - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ31_3 | ✅ | Connected to fan connector tachometer pin through NetJ31_3. | | 2 | 2 | 3.3VCC | ✅ | Connected to 3.3VCC to provide pull-up for tachometer signal. | </details> <details> <summary>R15 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED3_A | ✅ | Connected to LED3 anode for current limiting. | | 2 | 2 | VFAN | ✅ | Connected to VFAN supply to provide current for LED indicator. | </details> <details> <summary>R171 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | Fan3 | ✅ | Connected to Fan3 control signal input. | | 2 | 2 | GND | ✅ | Connected to ground to provide pull-down for Fan3 control signal. | </details> <details> <summary>J30 - CONN 3POS VERT 0.1" SHRD LOCKING PIP ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/sd/705430001_sd.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/0705430002) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S | VFAN | ✅ | Pin 1 is connected to VFAN but should be connected to the switched output from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. | | 2 | S | VFAN | ✅ | Pin 2 is correctly connected to VFAN to provide unswitched power supply to the fan. | | 3 | S | NetJ30_3 | ✅ | Pin 3 is correctly connected to the tachometer signal conditioning circuit through NetJ30_3. | </details> <details> <summary>Q13B - NCV8402AD ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | D | VFAN | ❌ | <details><summary>Drain pin is incorrectly connected directly to VFAN instead of to a switched output node. This is the root cause preventing the fan control circuit from functioning. The drain should connect to a switched node that includes J30 pin 1, LED4 cathode, and C209 pin 2.</summary>!thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="63.06,56.28,70.56,63.78" aspect-ratio="1.29" } <ul><li>Pin 5 is a Drain 2 terminal for channel 2 (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1">NCV8402ADDR2G</a>, page 1)</li><li>Pin 5 is connected to net VFAN (from schematic)</li><li>In a low-side switching configuration, the drain should connect to the load being switched (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=9">NCV8402ADDR2G</a>, page 9)</li><li>When the MOSFET turns on, it creates a low-resistance path from drain to source (ground) (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf">NCV8402ADDR2G</a>)</li><li>With the drain connected directly to VFAN, turning on the MOSFET would short VFAN directly to ground, which is incorrect (reasoning)</li><li>Comparing to Q12B (channel 2 of Q12), its drain pin 5 connects to NetC153_2 which goes to J22 pin 1 and LED2 cathode (from schematic)</li><li>Comparing to Q12A (channel 1 of Q12), its drain pin 7 connects to NetC154_2 which goes to J29 pin 1 and LED1 cathode (from schematic)</li><li>Comparing to Q13A (channel 1 of Q13), its drain pin 7 connects to NetC211_2 which goes to J31 pin 1 and LED3 cathode (from schematic)</li><li>Pin 5 should be connected to a switched output node (e.g., NetC209_2) that also connects to J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)</li><li>The current connection prevents the circuit from switching the fan power and would cause excessive current when the MOSFET turns on (reasoning)</li><li>The NCV8402AD has current limit protection that would likely activate, but this is still an incorrect and potentially damaging configuration (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=2">NCV8402ADDR2G</a>, page 2)</li></ul></details> | | 3 | S | GND | ✅ | Source pin is correctly connected to GND for low-side switching operation. | | 4 | G | NetQ13_4 | ✅ | Gate pin is correctly connected through a 100 ohm gate resistor (R181) to the buffer output (U2A pin 3). | </details> <details> <summary>LED4 - 5988110107F ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://s3-us-west-2.amazonaws.com/catsy.557/DIA_Selector_Guide_SMD_060820.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/5988110107F) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetLED4_A | ✅ | Anode is correctly connected through current limiting resistor R14 (4.7K) to VFAN. | | C | C | VFAN | ✅ | Cathode is connected to VFAN but should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. | </details> <details> <summary>D55 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | NetD55_A | ✅ | Anode is correctly connected to NetD55_A as part of the upper voltage clamp for the TACH_4 signal. | | K | K | 3.3VCC | ✅ | Cathode is correctly connected to 3.3VCC to clamp the tachometer signal to a safe voltage level. | </details> <details> <summary>D57 - BAT54WX ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/BAT54WX%28SOD-523%29.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | A | GND | ✅ | Anode is correctly connected to GND to provide lower voltage clamping for the TACH_4 signal. | | K | K | NetD55_A | ✅ | Cathode is correctly connected to NetD55_A to complete the lower clamp circuit for the tachometer signal. | </details> <details> <summary>U2A - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1OE | GND | ✅ | Output enable pin is correctly tied to GND to permanently enable the buffer output. | | 2 | 1A | Fan4 | ✅ | Input pin is correctly connected to the Fan4 control signal. | | 3 | 1Y | NetR181_1 | ✅ | Output pin is correctly connected through gate resistor R181 (100R) to drive the MOSFET gate of Q13B. | </details> <details> <summary>C213 - GRM155R71C104KA88D ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_4 | ✅ | Pin 1 is correctly connected to TACH_4 signal for filtering. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to complete the filter capacitor. | </details> <details> <summary>C209 - C0603TBD ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DNI-C0603TBD) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VFAN | ✅ | Both pins are connected to VFAN, but pin 2 should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. However, since this component is marked DNI (Do Not Install), the incorrect connection has no functional impact on the circuit. | | 2 | 2 | VFAN | ✅ | Both pins are connected to VFAN, but pin 2 should be connected to the switched output node from Q13B drain. This is a consequence of Q13B pin 5 being incorrectly connected to VFAN. However, since this component is marked DNI (Do Not Install), the incorrect connection has no functional impact on the circuit. | </details> <details> <summary>TP17 - TestPoint ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | TP | TP | VFAN | ✅ | Test point is correctly connected to VFAN for voltage measurement. | </details> <details> <summary>R181 - RES 100R 0402 1% ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetR181_1 | ✅ | Pin 1 is correctly connected to the buffer output (U2A pin 3) to provide gate drive to Q13B. | | 2 | 2 | NetQ13_4 | ✅ | Pin 2 is correctly connected to the gate of Q13B (pin 4) to drive the MOSFET. | </details> <details> <summary>R188 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TACH_4 | ✅ | Pin 1 is correctly connected to TACH_4 signal as part of the tachometer input circuit. | | 2 | 2 | NetD55_A | ✅ | Pin 2 is correctly connected to NetD55_A, forming part of the tachometer signal conditioning network. | </details> <details> <summary>R189 - RC0402FR-071KL ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetD55_A | ✅ | Pin 1 is correctly connected to NetD55_A as part of the tachometer signal conditioning circuit. | | 2 | 2 | NetJ30_3 | ✅ | Pin 2 is correctly connected to NetJ30_3, which connects to the tachometer pin of the fan connector. | </details> <details> <summary>R185 - RC0402FR-071K8L ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetJ30_3 | ✅ | Pin 1 is correctly connected to NetJ30_3, providing a pull-up for the tachometer signal. | | 2 | 2 | 3.3VCC | ✅ | Pin 2 is correctly connected to 3.3VCC to provide the pull-up voltage for the tachometer signal. | </details> <details> <summary>R14 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | NetLED4_A | ✅ | Pin 1 is correctly connected to the LED4 anode to provide current limiting. | | 2 | 2 | VFAN | ✅ | Pin 2 is correctly connected to VFAN to provide the supply voltage for the LED circuit. | </details> <details> <summary>R101 - 10k 1% 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | Fan4 | ✅ | Pin 1 is correctly connected to the Fan4 control signal to provide a pull-down. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND to complete the pull-down resistor. | </details> <details> <summary>U2E - SN74AHCT125 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn74ahct125) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SN74AHCT125RGYR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 7 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 14 | VCC | +5VCC | ✅ | VCC pin correctly connected to +5VCC with appropriate bypass capacitor C92. | | 15 | PAD | SNTP1 | ✅ | Thermal pad (PAD) is connected to SNTP1 net instead of GND. While thermal pads are typically grounded for proper heat dissipation, the presence of a deliberate text label 'SNTP1' at coordinates (110.49, 34.29) near the component suggests this connection may be intentional for testing or measurement purposes. This should be verified to ensure SNTP1 is either connected to GND elsewhere in the design or serves a specific intended function. | </details> <details> <summary>C92 - 100nF 0402 16V X7R ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM155R71C104KA88-01.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/GRM155R71C104KA88D) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor pin correctly connected to GND for bypass capacitor function. | | 2 | 2 | +5VCC | ✅ | Capacitor pin correctly connected to +5VCC, serving as bypass capacitor for U2E. | </details> <details> <summary>C106 - 100nF 6.3V X5R 0201 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/41/CL03A104KQ3NNNC_SS.pdf) [📤 Replace a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/CL03A104KQ3NNNC) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Capacitor pin correctly connected to GND for bypass capacitor function. | | 2 | 2 | 3.3VCC | ✅ | Capacitor pin correctly connected to 3.3VCC, serving as bypass capacitor for the 3.3V rail. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **S1** (1571610-2): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/1571610-2) - **P1** (2213S-08G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-08G) - **J20** (2213S-24G): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/2213S-24G) - **C153, C154, C209, C211** (DNI-C0603TBD): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/DNI-C0603TBD) - **JP1, JP2** (NOTAPART-Solder Bridge): [📤 Upload a datasheet](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NOTAPART-Solder%20Bridge) </details> Note: DRCY uses AI. Please verify the outputs.

Fans.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component D53, pin A: Anode is unconnected (floating), which is incorrect. This pin should be connected to GND to provide negative voltage clamping for the tachometer signal, matching the configuration of D52, D56, and D57 in the other three fan channels.

Pin A is the anode terminal of the Schottky diode (from datasheet BAT54WX-TP, page 1)
Pin A is connected to net unconnected-(NetD53_A), indicating it is floating (from schematic)
In the parallel channel 1 circuit, D52 has its anode connected to GND and cathode to NetD50_A (from schematic)
In channel 3, D56 has its anode connected to GND and cathode to NetD54_A (from schematic)
In channel 4, D57 has its anode connected to GND and cathode to NetD55_A (from schematic)
D51 and D53 should form a dual-diode clamp circuit for channel 2, with D51 clamping to 3.3VCC and D53 clamping to GND (reasoning)
The purpose of this diode is to clamp negative-going voltages on the tachometer signal to ground, protecting downstream circuitry (reasoning)
With the anode floating, D53 cannot perform its clamping function and the circuit lacks protection against negative voltage transients (reasoning)
The anode of D53 should be connected to GND to match the design pattern of the other three identical tachometer circuits (reasoning)

_{Replace a datasheet: 📤 D53}

**Component `D53`, pin `A`: Anode is unconnected (floating), which is incorrect. This pin should be connected to GND to provide negative voltage clamping for the tachometer signal, matching the configuration of D52, D56, and D57 in the other three fan channels.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="63.06,35.82,70.56,43.32" aspect-ratio="1.29" } - Pin A is the anode terminal of the Schottky diode *(from datasheet [BAT54WX-TP](<https://www.mccsemi.com/pdf/Products/BAT54WX(SOD-523).pdf#page=1>), page 1)* - Pin A is connected to net unconnected-(NetD53_A), indicating it is floating *(from schematic)* - In the parallel channel 1 circuit, D52 has its anode connected to GND and cathode to NetD50_A *(from schematic)* - In channel 3, D56 has its anode connected to GND and cathode to NetD54_A *(from schematic)* - In channel 4, D57 has its anode connected to GND and cathode to NetD55_A *(from schematic)* - D51 and D53 should form a dual-diode clamp circuit for channel 2, with D51 clamping to 3.3VCC and D53 clamping to GND *(reasoning)* - The purpose of this diode is to clamp negative-going voltages on the tachometer signal to ground, protecting downstream circuitry *(reasoning)* - With the anode floating, D53 cannot perform its clamping function and the circuit lacks protection against negative voltage transients *(reasoning)* - The anode of D53 should be connected to GND to match the design pattern of the other three identical tachometer circuits *(reasoning)* Replace a datasheet: [📤 D53](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/BAT54WX-TP)

👀 1

Fans.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component Q13B, pin 5: Drain pin is incorrectly connected directly to VFAN instead of to a switched output node. This is the root cause preventing the fan control circuit from functioning. The drain should connect to a switched node that includes J30 pin 1, LED4 cathode, and C209 pin 2.

Pin 5 is a Drain 2 terminal for channel 2 (from datasheet NCV8402ADDR2G, page 1)
Pin 5 is connected to net VFAN (from schematic)
In a low-side switching configuration, the drain should connect to the load being switched (from datasheet NCV8402ADDR2G, page 9)
When the MOSFET turns on, it creates a low-resistance path from drain to source (ground) (from datasheet NCV8402ADDR2G)
With the drain connected directly to VFAN, turning on the MOSFET would short VFAN directly to ground, which is incorrect (reasoning)
Comparing to Q12B (channel 2 of Q12), its drain pin 5 connects to NetC153_2 which goes to J22 pin 1 and LED2 cathode (from schematic)
Comparing to Q12A (channel 1 of Q12), its drain pin 7 connects to NetC154_2 which goes to J29 pin 1 and LED1 cathode (from schematic)
Comparing to Q13A (channel 1 of Q13), its drain pin 7 connects to NetC211_2 which goes to J31 pin 1 and LED3 cathode (from schematic)
Pin 5 should be connected to a switched output node (e.g., NetC209_2) that also connects to J30 pin 1, LED4 cathode, and C209 pin 2 (reasoning)
The current connection prevents the circuit from switching the fan power and would cause excessive current when the MOSFET turns on (reasoning)
The NCV8402AD has current limit protection that would likely activate, but this is still an incorrect and potentially damaging configuration (from datasheet NCV8402ADDR2G, page 2)

_{Replace a datasheet: 📤 Q13B}

**Component `Q13B`, pin `5`: Drain pin is incorrectly connected directly to VFAN instead of to a switched output node. This is the root cause preventing the fan control circuit from functioning. The drain should connect to a switched node that includes J30 pin 1, LED4 cathode, and C209 pin 2.** !thumbnail[](Fans.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="63.06,56.28,70.56,63.78" aspect-ratio="1.29" } - Pin 5 is a Drain 2 terminal for channel 2 *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=1>), page 1)* - Pin 5 is connected to net VFAN *(from schematic)* - In a low-side switching configuration, the drain should connect to the load being switched *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=9>), page 9)* - When the MOSFET turns on, it creates a low-resistance path from drain to source (ground) *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf>))* - With the drain connected directly to VFAN, turning on the MOSFET would short VFAN directly to ground, which is incorrect *(reasoning)* - Comparing to Q12B (channel 2 of Q12), its drain pin 5 connects to NetC153_2 which goes to J22 pin 1 and LED2 cathode *(from schematic)* - Comparing to Q12A (channel 1 of Q12), its drain pin 7 connects to NetC154_2 which goes to J29 pin 1 and LED1 cathode *(from schematic)* - Comparing to Q13A (channel 1 of Q13), its drain pin 7 connects to NetC211_2 which goes to J31 pin 1 and LED3 cathode *(from schematic)* - Pin 5 should be connected to a switched output node (e.g., NetC209_2) that also connects to J30 pin 1, LED4 cathode, and C209 pin 2 *(reasoning)* - The current connection prevents the circuit from switching the fan power and would cause excessive current when the MOSFET turns on *(reasoning)* - The NCV8402AD has current limit protection that would likely activate, but this is still an incorrect and potentially damaging configuration *(from datasheet [NCV8402ADDR2G](<https://www.onsemi.com/pdf/datasheet/ncv8402d-d.pdf#page=2>), page 2)* Replace a datasheet: [📤 Q13B](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/NCV8402ADDR2G)

Microcontroller.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component J4, pins 6, 8: TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.

Pin 6 is connected to the TDO/SWO net (from schematic)
Pin 8 is connected to the TDI net (from schematic)
The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic)
The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic)
ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning)
In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning)
The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning)
The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning)
The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning)
To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)

All affected pins

Component U11A, pins `29, 30`: JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net.

Pin 29 is PB29/TDI (Test Data In) (from schematic)
Pin 29 is connected to net TDO/SWO (from schematic)
Pin 30 is PB30/TDO/TRACESWO (Test Data Out) (from schematic)
Pin 30 is connected to net TDI (from schematic)
PB29 should function as TDI (Test Data In) per datasheet (from datasheet ATSAM3X8EA-AU, page 8)
PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet (from datasheet ATSAM3X8EA-AU, page 8)
JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) (from schematic)
JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) (from schematic)
The TDI and TDO pins are swapped, preventing proper JTAG debugging (reasoning)
Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO (reasoning)

Component J4, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.

Pin 6 is connected to the TDO/SWO net (from schematic)
Pin 8 is connected to the TDI net (from schematic)
The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI (from schematic)
The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO (from schematic)
ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) (reasoning)
In JTAG operation, TDO is an output from the target device and TDI is an input to the target device (reasoning)
The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations (reasoning)
The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) (reasoning)
The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap (reasoning)
To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) (reasoning)

Datasheets: 📄 J4 📄 U11A

_{Replace a datasheet: 📤 J4 📤 U11A}

**Component `J4`, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.** !thumbnail[](Microcontroller.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="39.19,70.36,46.69,78.76" aspect-ratio="1.55" } - Pin 6 is connected to the TDO/SWO net *(from schematic)* - Pin 8 is connected to the TDI net *(from schematic)* - The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI *(from schematic)* - The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO *(from schematic)* - ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) *(reasoning)* - In JTAG operation, TDO is an output from the target device and TDI is an input to the target device *(reasoning)* - The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations *(reasoning)* - The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) *(reasoning)* - The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap *(reasoning)* - To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U11A</code>, pins `29, 30`: JTAG data pins TDI and TDO are swapped. Pin 29 (TDI) connects to TDO/SWO net, and pin 30 (TDO) connects to TDI net.</summary> - Pin 29 is PB29/TDI (Test Data In) *(from schematic)* - Pin 29 is connected to net TDO/SWO *(from schematic)* - Pin 30 is PB30/TDO/TRACESWO (Test Data Out) *(from schematic)* - Pin 30 is connected to net TDI *(from schematic)* - PB29 should function as TDI (Test Data In) per datasheet *(from datasheet [ATSAM3X8EA-AU](<https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8>), page 8)* - PB30 should function as TDO/TRACESWO (Test Data Out) per datasheet *(from datasheet [ATSAM3X8EA-AU](<https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8>), page 8)* - JTAG connector J4 pin 6 connects to net TDO/SWO, which should go to pin 30 (TDO) *(from schematic)* - JTAG connector J4 pin 8 connects to net TDI, which should go to pin 29 (TDI) *(from schematic)* - The TDI and TDO pins are swapped, preventing proper JTAG debugging *(reasoning)* - Pin 29 should connect to net TDI, and pin 30 should connect to net TDO/SWO *(reasoning)* </details> <details> <summary>Component <code>J4</code>, pins `6, 8`: TDO and TDI signals are swapped. Pin 6 (TDO/SWO) is incorrectly connected to the microcontroller's TDI pin (PB29), and pin 8 (TDI) is incorrectly connected to the microcontroller's TDO pin (PB30). This will prevent JTAG debugging from functioning.</summary> - Pin 6 is connected to the TDO/SWO net *(from schematic)* - Pin 8 is connected to the TDI net *(from schematic)* - The TDO/SWO net connects to U11A pin 29 which is labeled PB29/TDI *(from schematic)* - The TDI net connects to U11A pin 30 which is labeled PB30/TDO/TRACESWO *(from schematic)* - ARM Cortex Debug Connector standard specifies pin 6 as TDO/SWO (Test Data Out / Serial Wire Output) and pin 8 as TDI (Test Data In) *(reasoning)* - In JTAG operation, TDO is an output from the target device and TDI is an input to the target device *(reasoning)* - The microcontroller pin 29 (PB29) is the TDI function (input to MCU) and pin 30 (PB30) is the TDO function (output from MCU) per standard ARM Cortex-M3 implementations *(reasoning)* - The connections are swapped: J4 pin 6 should connect to MCU TDO (pin 30) but connects to MCU TDI (pin 29), and J4 pin 8 should connect to MCU TDI (pin 29) but connects to MCU TDO (pin 30) *(reasoning)* - The presence of pull-up resistor R37 on the net labeled TDI (which actually connects to MCU TDO) is unusual, as TDI typically doesn't require a pull-up while TDO might benefit from one, further suggesting the swap *(reasoning)* - To correct this error, the TDO/SWO net should be connected to U11A pin 30 (PB30/TDO/TRACESWO) and the TDI net should be connected to U11A pin 29 (PB29/TDI) *(reasoning)* </details> </details> Datasheets: [📄 J4](https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/datasheet/boardwiretoboard/bwb_minitek127_btb.pdf) [📄 U11A](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf) Replace a datasheet: [📤 J4](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/20021121-00010C4LF) [📤 U11A](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU)

Power.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component U1, pin 2: VIN pin connected to VPWR rail with inadequate input decoupling capacitance. Datasheet recommends 10µF ceramic capacitor close to VIN pin, but only 10nF (C71) is nearby with bulk capacitance far away.

Pin 2 (VIN) is connected to net VPWR (from schematic)
VPWR is the main input power rail derived from VPWR_IN through fuse F2 (from schematic)
C71 (10nF 0402 50V X7R) is the closest capacitor to U1 on the VPWR net (from schematic)
C199, C202, and C203 (each 100nF 0603) are connected to VPWR but located far from U1 (from schematic)
Total ceramic capacitance on VPWR near U1 is approximately 10nF from C71 plus 300nF from distant capacitors, totaling ~310nF (reasoning)
Datasheet specifies input voltage range of 3.5V to 28V (from datasheet TPS54531DDAR, page 4)
Datasheet requires input decoupling capacitor with typical recommended value of 10µF high-quality ceramic type X5R or X7R (from datasheet TPS54531DDAR, page 14)
Datasheet design example uses two 4.7-µF capacitors for input decoupling, totaling 9.4µF (from datasheet TPS54531DDAR, page 15)
Datasheet layout guidelines state VIN pin must be bypassed to ground with low-ESR ceramic bypass capacitor with optimum placement closest to VIN pins (from datasheet TPS54531DDAR, page 23)
Datasheet emphasizes minimizing loop area formed by bypass capacitor connections, VIN pin, and anode of catch diode (from datasheet TPS54531DDAR, page 14)
The total input capacitance of approximately 310nF is significantly less than the recommended 10µF (approximately 32× smaller) (reasoning)
Insufficient input decoupling capacitance can lead to increased input voltage ripple, potential instability, poor transient response, increased EMI, and potential damage to the IC (reasoning)
Recommendation: Add 10µF or greater ceramic capacitor (X5R or X7R) directly at U1 VIN pin with minimal loop area to meet datasheet requirements (reasoning)

_{Replace a datasheet: 📤 U1}

**Component `U1`, pin `2`: VIN pin connected to VPWR rail with inadequate input decoupling capacitance. Datasheet recommends 10µF ceramic capacitor close to VIN pin, but only 10nF (C71) is nearby with bulk capacitance far away.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="50.79,50.99,58.29,58.49" aspect-ratio="1.29" } - Pin 2 (VIN) is connected to net VPWR *(from schematic)* - VPWR is the main input power rail derived from VPWR_IN through fuse F2 *(from schematic)* - C71 (10nF 0402 50V X7R) is the closest capacitor to U1 on the VPWR net *(from schematic)* - C199, C202, and C203 (each 100nF 0603) are connected to VPWR but located far from U1 *(from schematic)* - Total ceramic capacitance on VPWR near U1 is approximately 10nF from C71 plus 300nF from distant capacitors, totaling ~310nF *(reasoning)* - Datasheet specifies input voltage range of 3.5V to 28V *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=4>), page 4)* - Datasheet requires input decoupling capacitor with typical recommended value of 10µF high-quality ceramic type X5R or X7R *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14>), page 14)* - Datasheet design example uses two 4.7-µF capacitors for input decoupling, totaling 9.4µF *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=15>), page 15)* - Datasheet layout guidelines state VIN pin must be bypassed to ground with low-ESR ceramic bypass capacitor with optimum placement closest to VIN pins *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=23>), page 23)* - Datasheet emphasizes minimizing loop area formed by bypass capacitor connections, VIN pin, and anode of catch diode *(from datasheet [TPS54531DDAR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftps54531#page=14>), page 14)* - The total input capacitance of approximately 310nF is significantly less than the recommended 10µF (approximately 32× smaller) *(reasoning)* - Insufficient input decoupling capacitance can lead to increased input voltage ripple, potential instability, poor transient response, increased EMI, and potential damage to the IC *(reasoning)* - Recommendation: Add 10µF or greater ceramic capacitor (X5R or X7R) directly at U1 VIN pin with minimal loop area to meet datasheet requirements *(reasoning)* Replace a datasheet: [📤 U1](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/TPS54531DDAR)

Power.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component R115, pins 1, 2: 15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.

R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)
R115 pin 2 is connected to net 5V0_AUX (from schematic)
R115 value is 15kΩ per schematic (from schematic)
R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning)
Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)
Schematic text note indicates intended current limit is ~4A (from schematic)
For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)
To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)
With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)
Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)
The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)

All affected pins

Component U19, pin `5`: CMPREF pin connected to voltage divider formed by R115 (15kΩ) and R119 (4.7kΩ), but the resistor values are incorrect and set the current limit to approximately 2.4A instead of the intended ~4A per schematic text note. The voltage divider produces 1.193V instead of the required 2.0V for 4A threshold.

Pin 5 (CMPREF) is connected to net NetR115_1 (from schematic)
R115 (15kΩ) connects NetR115_1 to 5V0_AUX (from schematic)
R119 (4.7kΩ) connects NetR115_1 to GND (from schematic)
CMPREF is the input reference to the comparator per datasheet (from datasheet INA381A2IDSGR, page 3)
Voltage divider produces VCMPREF = 5V × (4.7kΩ / 19.7kΩ) = 1.193V (reasoning)
INA381A2 has a gain of 50 V/V per datasheet (from datasheet INA381A2IDSGR, page 5)
Current sense resistor R148 is 0.01Ω (10mΩ) (from schematic)
Current limit threshold = VCMPREF / (Gain × RSENSE) = 1.193V / (50 × 0.01Ω) = 2.386A (reasoning)
Schematic text note states 'Current Limiting for 5V rail (~4A)' (from schematic)
For 4A threshold: VCMPREF_needed = 4A × 0.01Ω × 50 = 2.0V (reasoning)
To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (reasoning)
Current resistor values result in approximately 60% of the intended current limit (2.4A vs 4A) (reasoning)
The incorrect threshold voltage is caused by wrong resistor values in R115 and R119 (reasoning)

Component R115, pins `1, 2`: 15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.

R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)
R115 pin 2 is connected to net 5V0_AUX (from schematic)
R115 value is 15kΩ per schematic (from schematic)
R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold (reasoning)
Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)
Schematic text note indicates intended current limit is ~4A (from schematic)
For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)
To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)
With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)
Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)
The 15kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)

Component R119, pins `1, 2`: 4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A.

R119 pin 1 is connected to net GND (from schematic)
R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) (from schematic)
R119 value is 4.7kΩ per schematic (from schematic)
R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold (reasoning)
Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit (reasoning)
Schematic text note indicates intended current limit is ~4A (from schematic)
For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V (reasoning)
To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) (reasoning)
With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold (reasoning)
Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold (reasoning)
The 4.7kΩ value is incorrect and results in only 60% of the intended current limit (reasoning)

Datasheets: 📄 R115 📄 U19 📄 R119

_{Replace a datasheet: 📤 R115 📤 R119 📤 U19}

**Component `R115`, pins `1, 2`: 15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="40.80,32.18,48.30,40.85" aspect-ratio="1.29" } - R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) *(from schematic)* - R115 pin 2 is connected to net 5V0_AUX *(from schematic)* - R115 value is 15kΩ per schematic *(from schematic)* - R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold *(reasoning)* - Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit *(reasoning)* - Schematic text note indicates intended current limit is ~4A *(from schematic)* - For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V *(reasoning)* - To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) *(reasoning)* - With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold *(reasoning)* - Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold *(reasoning)* - The 15kΩ value is incorrect and results in only 60% of the intended current limit *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>U19</code>, pin `5`: CMPREF pin connected to voltage divider formed by R115 (15kΩ) and R119 (4.7kΩ), but the resistor values are incorrect and set the current limit to approximately 2.4A instead of the intended ~4A per schematic text note. The voltage divider produces 1.193V instead of the required 2.0V for 4A threshold.</summary> - Pin 5 (CMPREF) is connected to net NetR115_1 *(from schematic)* - R115 (15kΩ) connects NetR115_1 to 5V0_AUX *(from schematic)* - R119 (4.7kΩ) connects NetR115_1 to GND *(from schematic)* - CMPREF is the input reference to the comparator per datasheet *(from datasheet [INA381A2IDSGR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fina381#page=3>), page 3)* - Voltage divider produces VCMPREF = 5V × (4.7kΩ / 19.7kΩ) = 1.193V *(reasoning)* - INA381A2 has a gain of 50 V/V per datasheet *(from datasheet [INA381A2IDSGR](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fina381#page=5>), page 5)* - Current sense resistor R148 is 0.01Ω (10mΩ) *(from schematic)* - Current limit threshold = VCMPREF / (Gain × RSENSE) = 1.193V / (50 × 0.01Ω) = 2.386A *(reasoning)* - Schematic text note states 'Current Limiting for 5V rail (~4A)' *(from schematic)* - For 4A threshold: VCMPREF_needed = 4A × 0.01Ω × 50 = 2.0V *(reasoning)* - To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 *(reasoning)* - Current resistor values result in approximately 60% of the intended current limit (2.4A vs 4A) *(reasoning)* - The incorrect threshold voltage is caused by wrong resistor values in R115 and R119 *(reasoning)* </details> <details> <summary>Component <code>R115</code>, pins `1, 2`: 15kΩ resistor forms upper part of CMPREF voltage divider between 5V0_AUX and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 7kΩ (with R119 = 4.7kΩ) or R119 should be changed to 10kΩ (with R115 = 15kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary> - R115 pin 1 is connected to net NetR115_1 (U19 CMPREF pin) *(from schematic)* - R115 pin 2 is connected to net 5V0_AUX *(from schematic)* - R115 value is 15kΩ per schematic *(from schematic)* - R115 forms voltage divider with R119 (4.7kΩ) to set CMPREF threshold *(reasoning)* - Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit *(reasoning)* - Schematic text note indicates intended current limit is ~4A *(from schematic)* - For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V *(reasoning)* - To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) *(reasoning)* - With R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold *(reasoning)* - Alternatively, with R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold *(reasoning)* - The 15kΩ value is incorrect and results in only 60% of the intended current limit *(reasoning)* </details> <details> <summary>Component <code>R119</code>, pins `1, 2`: 4.7kΩ resistor forms lower part of CMPREF voltage divider between GND and NetR115_1, but the value is incorrect for achieving the intended 4A current limit. Should be approximately 10kΩ (with R115 = 15kΩ) or R115 should be changed to 7kΩ (with R119 = 4.7kΩ) to achieve the required 2.0V CMPREF threshold for 4A.</summary> - R119 pin 1 is connected to net GND *(from schematic)* - R119 pin 2 is connected to net NetR115_1 (U19 CMPREF pin) *(from schematic)* - R119 value is 4.7kΩ per schematic *(from schematic)* - R119 forms voltage divider with R115 (15kΩ) to set CMPREF threshold *(reasoning)* - Current resistor values produce VCMPREF = 1.193V, resulting in 2.4A current limit *(reasoning)* - Schematic text note indicates intended current limit is ~4A *(from schematic)* - For 4A threshold with INA381A2 gain of 50 V/V and R148 = 10mΩ, VCMPREF should be 2.0V *(reasoning)* - To achieve 2.0V from 5V supply, voltage divider ratio should be 0.4 (R119/(R115+R119) = 0.4) *(reasoning)* - With R115 = 15kΩ, R119 should be approximately 10kΩ to achieve 4A threshold *(reasoning)* - Alternatively, with R119 = 4.7kΩ, R115 should be approximately 7.05kΩ to achieve 4A threshold *(reasoning)* - The 4.7kΩ value is incorrect and results in only 60% of the intended current limit *(reasoning)* </details> </details> Datasheets: [📄 R115](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/39/RC_Series_ds.pdf) [📄 U19](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fina381) [📄 R119](https://yageogroup.com/content/datasheet/asset/file/PYU-RC_GROUP_51_ROHS_L) Replace a datasheet: [📤 R115](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC1005F153CS) [📤 R119](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/RC0402FR-074K7L) [📤 U19](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/INA381A2IDSGR)

Power.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component D21, pins A, K: The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.

Pin A (Anode) is connected to net VMOTE (from schematic)
Pin K (Cathode) is connected to net GND (from schematic)
VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic)
SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet SMAJ24A, page 1)
The cathode is marked with a color band in uni-directional configuration (from datasheet SMAJ24A, page 1)
For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet SMAJ24A, page 3)
During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning)
With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning)
All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic)
D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic)
D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic)
D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic)
The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning)
The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)

All affected pins

Component D21, pins `A, K`: The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.

Pin A (Anode) is connected to net VMOTE (from schematic)
Pin K (Cathode) is connected to net GND (from schematic)
VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation (from schematic)
SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage (from datasheet SMAJ24A, page 1)
The cathode is marked with a color band in uni-directional configuration (from datasheet SMAJ24A, page 1)
For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground (from datasheet SMAJ24A, page 3)
During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs (reasoning)
With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground (reasoning)
All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail (from schematic)
D22 has anode to GND and cathode to VPWR, which is the correct configuration (from schematic)
D43 has anode to GND and cathode to VMOTA, which is the correct configuration (from schematic)
D78 has anode to GND and cathode to VBED, which is the correct configuration (from schematic)
The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice (reasoning)
The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND (reasoning)

Component J3, pin `1`: Connected to VMOTE net, which powers motors 5-8. However, the TVS diode D21 protecting this rail is connected backwards (anode on VMOTE, cathode on GND), which will not provide proper overvoltage protection.

Pin 1 is connected to the VMOTE net (from schematic)
VMOTE powers motors 5-8 based on nearby text annotation (from schematic)
VMOTE is protected by TVS diode D21 (SMAJ24A) (from schematic)
D21 has its anode (A) connected to VMOTE and cathode (K) connected to GND (from schematic)
For proper overvoltage protection, unidirectional TVS diodes should have cathode on the power rail and anode on ground to clamp positive voltage transients (reasoning)
All other TVS diodes on the board (D43 on VMOTA, D22 on VPWR, D78 on VBED) are correctly oriented with cathode on power rail and anode on ground (from schematic)
D21 is connected backwards compared to the other TVS diodes, which will prevent it from providing proper overvoltage protection and may conduct in normal operation (reasoning)
D21 should be reversed to have cathode on VMOTE and anode on GND (reasoning)
The barrier block is rated for 20A at 150V (UL Class C) and 10A at 300V (UL Class D), which is adequate for 12-24VDC motor power input (from datasheet 4DB-P108-10)
Wire range is 12-22 AWG, suitable for high current motor power connections (from datasheet 4DB-P108-10)

Datasheets: 📄 D21 📄 J3

_{Replace a datasheet: 📤 D21 📤 J3}

**Component `D21`, pins `A, K`: The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.** !thumbnail[](Power.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="2.64,54.99,10.14,63.66" aspect-ratio="1.29" } - Pin A (Anode) is connected to net VMOTE *(from schematic)* - Pin K (Cathode) is connected to net GND *(from schematic)* - VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation *(from schematic)* - SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The cathode is marked with a color band in uni-directional configuration *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=3>), page 3)* - During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs *(reasoning)* - With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground *(reasoning)* - All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail *(from schematic)* - D22 has anode to GND and cathode to VPWR, which is the correct configuration *(from schematic)* - D43 has anode to GND and cathode to VMOTA, which is the correct configuration *(from schematic)* - D78 has anode to GND and cathode to VBED, which is the correct configuration *(from schematic)* - The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice *(reasoning)* - The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>D21</code>, pins `A, K`: The anode and cathode connections are reversed. The anode is connected to VMOTE and the cathode is connected to GND, which is backwards for a uni-directional TVS diode and will cause it to be forward-biased during normal operation.</summary> - Pin A (Anode) is connected to net VMOTE *(from schematic)* - Pin K (Cathode) is connected to net GND *(from schematic)* - VMOTE is the motor power supply rail for motors 5-8, as indicated by nearby text annotation *(from schematic)* - SMAJ24A is a uni-directional TVS diode with a 24V reverse stand-off voltage *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - The cathode is marked with a color band in uni-directional configuration *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=1>), page 1)* - For uni-directional TVS diodes, the cathode should be connected to the voltage rail being protected and the anode should be connected to ground *(from datasheet [SMAJ24A](<https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d#page=3>), page 3)* - During normal operation, a TVS diode should be reverse-biased with the cathode at higher voltage than the anode to remain non-conducting until a transient event occurs *(reasoning)* - With the current configuration, D21 is forward-biased during normal operation, which would cause continuous conduction and effectively short VMOTE to ground *(reasoning)* - All other SMAJ24A diodes in the design (D22, D43, D78) have the correct polarity with anode to GND and cathode to the protected rail *(from schematic)* - D22 has anode to GND and cathode to VPWR, which is the correct configuration *(from schematic)* - D43 has anode to GND and cathode to VMOTA, which is the correct configuration *(from schematic)* - D78 has anode to GND and cathode to VBED, which is the correct configuration *(from schematic)* - The inconsistency between D21 and the other identical TVS diodes indicates this is an error rather than an intentional design choice *(reasoning)* - The connections should be corrected so that the cathode (K) connects to VMOTE and the anode (A) connects to GND *(reasoning)* </details> <details> <summary>Component <code>J3</code>, pin `1`: Connected to VMOTE net, which powers motors 5-8. However, the TVS diode D21 protecting this rail is connected backwards (anode on VMOTE, cathode on GND), which will not provide proper overvoltage protection.</summary> - Pin 1 is connected to the VMOTE net *(from schematic)* - VMOTE powers motors 5-8 based on nearby text annotation *(from schematic)* - VMOTE is protected by TVS diode D21 (SMAJ24A) *(from schematic)* - D21 has its anode (A) connected to VMOTE and cathode (K) connected to GND *(from schematic)* - For proper overvoltage protection, unidirectional TVS diodes should have cathode on the power rail and anode on ground to clamp positive voltage transients *(reasoning)* - All other TVS diodes on the board (D43 on VMOTA, D22 on VPWR, D78 on VBED) are correctly oriented with cathode on power rail and anode on ground *(from schematic)* - D21 is connected backwards compared to the other TVS diodes, which will prevent it from providing proper overvoltage protection and may conduct in normal operation *(reasoning)* - D21 should be reversed to have cathode on VMOTE and anode on GND *(reasoning)* - The barrier block is rated for 20A at 150V (UL Class C) and 10A at 300V (UL Class D), which is adequate for 12-24VDC motor power input *(from datasheet [4DB-P108-10](<https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English>))* - Wire range is 12-22 AWG, suitable for high current motor power connections *(from datasheet [4DB-P108-10](<https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English>))* </details> </details> Datasheets: [📄 D21](https://www.littelfuse.com/assetdocs/tvs-diodes-smaj-datasheet?assetguid=13c2a823-03b8-4d1f-9ddc-9b44670aed9d) [📄 J3](https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2-1437667-4&DocType=Customer+Drawing&DocLang=English) Replace a datasheet: [📤 D21](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/SMAJ24A) [📤 J3](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/4DB-P108-10)

👀 1

allspice-carah commented

2026-03-17 21:28:39 +00:00

Author

Owner

Can we identify the root cause of this mix up and create an issue? @AllSpiceAlice

USB.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component U11B, pins 37, 38, 42, 43: The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.

Pin 37 (DHSDP) connects directly to net UMCU_P (from schematic)
Pin 38 (DHSDM) connects directly to net UMCU_N (from schematic)
Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P (from schematic)
Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N (from schematic)
UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 (from schematic)
DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8)
DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet (from datasheet ATSAM3X8EA-AU, page 8)
The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) (from schematic)
The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together (from datasheet ATSAM3X8EA-AU, page 1401-1402)
Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation (reasoning)
The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω (reasoning)
Excessive series resistance will degrade USB signal integrity and may cause communication failures (reasoning)
Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected (reasoning)
Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N (reasoning)
Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM (reasoning)

_{Replace a datasheet: 📤 U11B}

**Component `U11B`, pins `37, 38, 42, 43`: The USB High Speed pins (DHSDP/DHSDM on pins 37/38) and Full Speed pins (DFSDP/DFSDM on pins 42/43) are incorrectly connected together through the UMCU_P/UMCU_N nets. For full-speed USB operation with the ADuM3160 isolator, only the full-speed pins should be used. Additionally, the dual series resistors (R47+R48 and R45+R42) create excessive 48Ω series resistance.** !thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="34.89,19.25,42.39,31.45" aspect-ratio="1.29" } - Pin 37 (DHSDP) connects directly to net UMCU_P *(from schematic)* - Pin 38 (DHSDM) connects directly to net UMCU_N *(from schematic)* - Pin 42 (DFSDP) connects through R48 (24Ω) to net UMCU_P *(from schematic)* - Pin 43 (DFSDM) connects through R42 (24Ω) to net UMCU_N *(from schematic)* - UMCU_P and UMCU_N also connect through R47 and R45 (24Ω each) to the USB isolator U9 *(from schematic)* - DHSDP and DHSDM are USB High Speed Data +/- pins for 480Mbps operation per the datasheet *(from datasheet [ATSAM3X8EA-AU](<https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8>), page 8)* - DFSDP and DFSDM are USB Full Speed Data +/- pins for 12Mbps operation per the datasheet *(from datasheet [ATSAM3X8EA-AU](<https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=8>), page 8)* - The USB isolator U9 (ADuM3160) is specified for 12Mbps operation, which is full-speed USB, not high-speed (480Mbps) *(from schematic)* - The SAM3X has separate high-speed and full-speed USB interfaces that operate independently and should not be connected together *(from datasheet [ATSAM3X8EA-AU](<https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf#page=1401-1402>), page 1401-1402)* - Connecting both USB interfaces together violates USB 2.0 design practices and will cause improper operation *(reasoning)* - The dual series resistors create 48Ω total resistance (R47+R48 on D+ and R45+R42 on D-), which exceeds the typical USB 2.0 full-speed requirement of 22-33Ω *(reasoning)* - Excessive series resistance will degrade USB signal integrity and may cause communication failures *(reasoning)* - Correct design: Disconnect pins 37 and 38 (DHSDP/DHSDM) from UMCU_P/UMCU_N nets and leave unconnected *(reasoning)* - Correct design: Remove or mark R48 and R42 as DNI, connecting DFSDP/DFSDM directly to UMCU_P/UMCU_N *(reasoning)* - Correct design: USB path should be: Isolator → R47/R45 (24Ω) → UMCU_P/UMCU_N → DFSDP/DFSDM *(reasoning)* Replace a datasheet: [📤 U11B](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/ATSAM3X8EA-AU)

USB.SchDoc

DRCYAI commented

2026-03-17 19:59:49 +00:00

Component C41, pins 1, 2: Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.

Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic)
Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic)
This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1)
The connection topology is correct for a crystal oscillator load capacitor (reasoning)
The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1)
The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet 405C35B12M00000, page 1)
For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning)
With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning)
This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning)
To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning)
The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)
Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)

All affected pins

Component C41, pins `1, 2`: Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.

Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 (from schematic)
Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) (from schematic)
This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1)
The connection topology is correct for a crystal oscillator load capacitor (reasoning)
The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1)
The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format (from datasheet 405C35B12M00000, page 1)
For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray (reasoning)
With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF (reasoning)
This 4.5pF effective load capacitance is significantly less than the required 13pF specification (reasoning)
To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 (reasoning)
The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)
Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)

Component C42, pins `1, 2`: Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.

Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 (from schematic)
Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) (from schematic)
This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift (from datasheet 06031A3R0BAT2A, page 1)
The connection topology is correct for a crystal oscillator load capacitor (reasoning)
The capacitor value is 3pF ±0.1pF (from datasheet 06031A3R0BAT2A, page 1)
C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required (reasoning)
The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side (from datasheet 405C35B12M00000, page 1)
The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure (reasoning)
Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification (reasoning)

Datasheets: 📄 C41

_{Replace a datasheet: 📤 C41 📤 C42}

**Component `C41`, pins `1, 2`: Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.** !thumbnail[](USB.SchDoc){ diff="AllSpice-Demos/Archimajor-DRCY-Demo:26590581be02618ce3f47deedb643c2d47d4182d...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" variant="default" view-coords="16.72,30.18,24.22,38.15" aspect-ratio="1.29" } - Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 *(from schematic)* - Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) *(from schematic)* - This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - The connection topology is correct for a crystal oscillator load capacitor *(reasoning)* - The capacitor value is 3pF ±0.1pF *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format *(from datasheet [405C35B12M00000](<https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1>), page 1)* - For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray *(reasoning)* - With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF *(reasoning)* - This 4.5pF effective load capacitance is significantly less than the required 13pF specification *(reasoning)* - To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 *(reasoning)* - The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure *(reasoning)* - Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>C41</code>, pins `1, 2`: Load capacitor is correctly connected between crystal pin 3 (XOUT side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary> - Pin 1 is connected to GND and pin 2 is connected to net NetC41_2 *(from schematic)* - Net NetC41_2 connects to crystal X1 pin 3 (C2) and microcontroller U11B pin 35 (XOUT) *(from schematic)* - This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - The connection topology is correct for a crystal oscillator load capacitor *(reasoning)* - The capacitor value is 3pF ±0.1pF *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - The crystal part number 405C35B12M00000 contains load capacitance code 'B' (13pF) in its ordering code format *(from datasheet [405C35B12M00000](<https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1>), page 1)* - For a crystal with 13pF load capacitance specification, the load capacitor formula is CL = (C1 × C2)/(C1 + C2) + Cstray *(reasoning)* - With C1 = C2 = 3pF and typical Cstray ≈ 3pF, the effective load capacitance is approximately (3×3)/(3+3) + 3 = 4.5pF *(reasoning)* - This 4.5pF effective load capacitance is significantly less than the required 13pF specification *(reasoning)* - To achieve 13pF load capacitance with typical 3pF stray capacitance, load capacitors should be approximately 20pF each: 13 = (20×20)/(20+20) + 3 = 10 + 3 *(reasoning)* - The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure *(reasoning)* - Recommendation: Replace C41 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification *(reasoning)* </details> <details> <summary>Component <code>C42</code>, pins `1, 2`: Load capacitor is correctly connected between crystal pin 1 (XIN side) and ground, but the 3pF value is significantly undersized for the crystal's 13pF load capacitance specification. Should be approximately 20pF.</summary> - Pin 1 is connected to GND and pin 2 is connected to net NetC42_2 *(from schematic)* - Net NetC42_2 connects to crystal X1 pin 1 (C1) and microcontroller U11B pin 36 (XIN) *(from schematic)* - This capacitor is a C0G (NP0) dielectric type, which is appropriate for crystal oscillator circuits due to its excellent temperature stability (0±30ppm/°C) and low drift *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - The connection topology is correct for a crystal oscillator load capacitor *(reasoning)* - The capacitor value is 3pF ±0.1pF *(from datasheet [06031A3R0BAT2A](<https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf#page=1>), page 1)* - C42 has the same load capacitance mismatch issue as C41 - both are undersized at 3pF when approximately 20pF is required *(reasoning)* - The crystal part number 405C35B12M00000 specifies 13pF load capacitance, requiring approximately 20pF load capacitors on each side *(from datasheet [405C35B12M00000](<https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Crystals/crystals-405-datasheet.pdf#page=1>), page 1)* - The undersized load capacitors will cause the crystal to oscillate at a higher frequency than specified, potentially causing timing errors, frequency drift, or oscillation startup failure *(reasoning)* - Recommendation: Replace C42 with a 20pF or 22pF C0G (NP0) capacitor to match the crystal's 13pF load capacitance specification *(reasoning)* </details> </details> Datasheets: [📄 C41](https://datasheets.kyocera-avx.com/C0GNP0-Dielectric.pdf) Replace a datasheet: [📤 C41](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/06031A3R0BAT2A) [📤 C42](https://hub.allspice.io/AllSpice-Demos/Archimajor-DRCY-Demo/_upload/develop/.allspice/datasheets/06031A3R0BAT2A)

allspice-carah added the

labels 2026-03-17 21:04:04 +00:00

allspice-carah requested review from allspice-thomas 2026-03-17 21:04:15 +00:00

allspice-carah requested review from AllSpiceAlice 2026-03-17 21:04:26 +00:00

allspice-carah requested review from allspice-nick 2026-03-17 21:04:30 +00:00

allspice-carah reviewed 2026-03-17 21:18:25 +00:00

Microcontroller.SchDoc

allspice-carah commented

2026-03-17 21:18:25 +00:00

Author

Owner

@AllSpiceAlice why are we removing this cap?

!thumbnail[](Microcontroller.SchDoc){ view-coords="4.9,48.2,12.6,58.5" variant="default" aspect-ratio="1.514" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" } @AllSpiceAlice why are we removing this cap?

allspice-carah reviewed 2026-03-17 21:20:52 +00:00

Archimajor.PcbDoc

allspice-carah commented

2026-03-17 21:20:51 +00:00

Author

Owner

@allspice-nick can you double check the added trace here?

!thumbnail[](Archimajor.PcbDoc){ view-coords="14.4,16.7,19.3,27.8" layers="82,81,74,57,33,35,37,1,41,40,2,39,32,38,34" variant="default" aspect-ratio="1.339" diff="AllSpice-Demos/Archimajor-DRCY-Demo:9ecce85a87495918c7559a01f7af99f93647b863...b09435216bda90650e7fdf6b009674871e52ddc7" pr="2" diff-visibility="full" } @allspice-nick can you double check the added trace here?