Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cndiscrete/trans#20mosfet/entity/verilog.v
2025-01-07 19:29:47 -08:00

15 lines
180 B
Verilog

// generated by newgenasym Mon Oct 10 17:27:26 2016
module \trans#20mosfet (d, g, s);
inout d;
inout g;
inout s;
initial
begin
end
endmodule