12 lines
277 B
VHDL
12 lines
277 B
VHDL
-- generated by newgenasym Mon Oct 10 17:27:26 2016
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \trans mosfet\ is
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port (
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D: INOUT STD_LOGIC;
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G: INOUT STD_LOGIC;
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S: INOUT STD_LOGIC);
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end \trans mosfet\;
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