18 lines
277 B
Verilog
18 lines
277 B
Verilog
// generated by newgenasym Mon May 11 17:25:27 2015
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module \854s01i (clk_sel, npclk, nq, pclk, q, reserved);
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input clk_sel;
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input [1:0] npclk;
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output nq;
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input [1:0] pclk;
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output q;
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input reserved;
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initial
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begin
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end
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endmodule
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