Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cninterface/854s01i/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

15 lines
409 B
VHDL

-- generated by newgenasym Mon May 11 17:25:27 2015
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \854s01i\ is
port (
CLK_SEL: IN STD_LOGIC;
NPCLK: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
NQ: OUT STD_LOGIC;
PCLK: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Q: OUT STD_LOGIC;
RESERVED: IN STD_LOGIC);
end \854s01i\;