24 lines
396 B
Verilog
24 lines
396 B
Verilog
// generated by newgenasym Thu Nov 13 16:34:18 2014
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module adclk948 (clk0, \clk0* , clk1, \clk1* , in_sel, q, \q* , vref0, vref1, vt0,
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vt1);
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input clk0;
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input \clk0* ;
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input clk1;
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input \clk1* ;
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input in_sel;
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input [7:0] q;
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input [7:0] \q* ;
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input vref0;
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input vref1;
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input vt0;
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input vt1;
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initial
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begin
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end
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endmodule
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