20 lines
577 B
VHDL
20 lines
577 B
VHDL
-- generated by newgenasym Thu Nov 13 16:34:18 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ADCLK948 is
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port (
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CLK0: IN STD_LOGIC;
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\clk0*\: IN STD_LOGIC;
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CLK1: IN STD_LOGIC;
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\clk1*\: IN STD_LOGIC;
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IN_SEL: IN STD_LOGIC;
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Q: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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\q*\: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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VREF0: IN STD_LOGIC;
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VREF1: IN STD_LOGIC;
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VT0: IN STD_LOGIC;
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VT1: IN STD_LOGIC);
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end ADCLK948;
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