Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnlinear/ltc2991/entity/verilog.v
2025-01-07 19:29:47 -08:00

26 lines
393 B
Verilog

// generated by newgenasym Sun May 29 16:39:47 2016
module ltc2991 (adr0, adr1, adr2, pwm, scl, sda, v1, v2, v3, v4, v5, v6, v7, v8);
input adr0;
input adr1;
input adr2;
input pwm;
input scl;
inout sda;
input v1;
input v2;
input v3;
input v4;
input v5;
input v6;
input v7;
input v8;
initial
begin
end
endmodule