23 lines
637 B
VHDL
23 lines
637 B
VHDL
-- generated by newgenasym Sun May 29 16:39:47 2016
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity LTC2991 is
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port (
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ADR0: IN STD_LOGIC;
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ADR1: IN STD_LOGIC;
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ADR2: IN STD_LOGIC;
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PWM: IN STD_LOGIC;
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SCL: IN STD_LOGIC;
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SDA: INOUT STD_LOGIC;
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V1: IN STD_LOGIC;
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V2: IN STD_LOGIC;
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V3: IN STD_LOGIC;
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V4: IN STD_LOGIC;
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V5: IN STD_LOGIC;
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V6: IN STD_LOGIC;
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V7: IN STD_LOGIC;
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V8: IN STD_LOGIC);
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end LTC2991;
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