Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnlinear/pth08t210w/entity/verilog.v
2025-01-07 19:29:47 -08:00

21 lines
351 B
Verilog

// generated by newgenasym Tue Feb 07 15:31:37 2023
module pth08t210w (gnd, sensm, sensp, track, turbotrans, uvlo, vadj, vi, vo);
input [3:0] gnd;
input sensm;
input sensp;
inout track;
input turbotrans;
output uvlo;
inout vadj;
input [1:0] vi;
input [1:0] vo;
initial
begin
end
endmodule