Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpassive/rsmd0402/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

14 lines
336 B
VHDL

-- generated by newgenasym Fri May 25 18:22:12 2012
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity RSMD0402 is
generic (
size:positive:= 1
);
port (
A: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
B: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end RSMD0402;