Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpassive/rsmd0603/entity/verilog.v
2025-01-07 19:29:47 -08:00

15 lines
205 B
Verilog

// generated by newgenasym Fri Oct 04 17:52:53 2013
module rsmd0603 (a, b);
parameter size = 1;
inout [size-1:0] a;
inout [size-1:0] b;
initial
begin
end
endmodule