14 lines
336 B
VHDL
14 lines
336 B
VHDL
-- generated by newgenasym Fri Oct 04 17:52:53 2013
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity RSMD0603 is
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generic (
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size:positive:= 1
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);
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port (
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A: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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B: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end RSMD0603;
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