13 lines
265 B
VHDL
13 lines
265 B
VHDL
-- generated by newgenasym Fri Jun 26 11:16:55 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity TP is
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generic (
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size:positive:= 1
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);
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port (
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A: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end TP;
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